📄 display.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\sz-eda\edap\ceda\led\display.rpt
display
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 2/ 96( 2%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 6/16( 37%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 1/ 48( 2%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\sz-eda\edap\ceda\led\display.rpt
display
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK2
DFF 5 vv0
INPUT 1 CLK1
Device-Specific Information: e:\sz-eda\edap\ceda\led\display.rpt
display
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 8 RESET
Device-Specific Information: e:\sz-eda\edap\ceda\led\display.rpt
display
** EQUATIONS **
CLK1 : INPUT;
CLK2 : INPUT;
RESET : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = counter0;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = counter1;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = counter2;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = counter3;
-- Node name is 'A4'
-- Equation name is 'A4', type is output
A4 = PAGE0;
-- Node name is 'A5'
-- Equation name is 'A5', type is output
A5 = PAGE1;
-- Node name is 'A6'
-- Equation name is 'A6', type is output
A6 = PAGE2;
-- Node name is 'A7'
-- Equation name is 'A7', type is output
A7 = PAGE3;
-- Node name is '~19~1' = 'counter0~1'
-- Equation name is '~19~1', location is LC5_B19, type is buried.
-- synthesized logic cell
_LC5_B19 = DFFE(!_LC5_B19, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
-- Node name is ':19' = 'counter0'
-- Equation name is 'counter0', location is LC2_A21, type is buried.
counter0 = DFFE(!counter0, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
-- Node name is '~18~1' = 'counter1~1'
-- Equation name is '~18~1', location is LC7_A21, type is buried.
-- synthesized logic cell
_LC7_A21 = DFFE( _EQ001, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ001 = !counter0 & _LC7_A21
# counter0 & !_LC7_A21;
-- Node name is ':18' = 'counter1'
-- Equation name is 'counter1', location is LC5_A21, type is buried.
counter1 = DFFE( _EQ002, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ002 = !counter0 & counter1
# counter0 & !counter1;
-- Node name is '~17~1' = 'counter2~1'
-- Equation name is '~17~1', location is LC1_A21, type is buried.
-- synthesized logic cell
_LC1_A21 = DFFE( _EQ003, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ003 = !counter1 & _LC1_A21
# !counter0 & _LC1_A21
# counter0 & counter1 & !_LC1_A21;
-- Node name is ':17' = 'counter2'
-- Equation name is 'counter2', location is LC3_A21, type is buried.
counter2 = DFFE( _EQ004, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ004 = !counter1 & counter2
# !counter0 & counter2
# counter0 & counter1 & !counter2;
-- Node name is '~16~1' = 'counter3~1'
-- Equation name is '~16~1', location is LC4_A21, type is buried.
-- synthesized logic cell
_LC4_A21 = DFFE( _EQ005, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ005 = !counter1 & _LC4_A21
# !counter0 & _LC4_A21
# !counter2 & _LC4_A21
# counter0 & counter1 & counter2 & !_LC4_A21;
-- Node name is ':16' = 'counter3'
-- Equation name is 'counter3', location is LC8_A21, type is buried.
counter3 = DFFE( _EQ006, GLOBAL( CLK2), GLOBAL(!RESET), VCC, VCC);
_EQ006 = !counter1 & counter3
# !counter0 & counter3
# !counter2 & counter3
# counter0 & counter1 & counter2 & !counter3;
-- Node name is 'LEDW0'
-- Equation name is 'LEDW0', type is output
LEDW0 = _LC5_B19;
-- Node name is 'LEDW1'
-- Equation name is 'LEDW1', type is output
LEDW1 = _LC7_A21;
-- Node name is 'LEDW2'
-- Equation name is 'LEDW2', type is output
LEDW2 = _LC1_A21;
-- Node name is 'LEDW3'
-- Equation name is 'LEDW3', type is output
LEDW3 = _LC4_A21;
-- Node name is ':27' = 'PAGE0'
-- Equation name is 'PAGE0', location is LC1_B2, type is buried.
PAGE0 = DFFE(!PAGE0, vv0, VCC, VCC, VCC);
-- Node name is ':26' = 'PAGE1'
-- Equation name is 'PAGE1', location is LC4_B2, type is buried.
PAGE1 = DFFE( _EQ007, vv0, VCC, VCC, VCC);
_EQ007 = !PAGE0 & PAGE1
# PAGE0 & !PAGE1;
-- Node name is ':25' = 'PAGE2'
-- Equation name is 'PAGE2', location is LC8_B2, type is buried.
PAGE2 = DFFE( _EQ008, vv0, VCC, VCC, VCC);
_EQ008 = !PAGE1 & PAGE2
# !PAGE0 & PAGE2
# PAGE0 & PAGE1 & !PAGE2;
-- Node name is ':24' = 'PAGE3'
-- Equation name is 'PAGE3', location is LC6_B2, type is buried.
PAGE3 = DFFE( _EQ009, vv0, VCC, VCC, VCC);
_EQ009 = !PAGE1 & PAGE3
# !PAGE0 & PAGE3
# !PAGE2 & PAGE3
# PAGE0 & PAGE1 & PAGE2 & !PAGE3;
-- Node name is ':22' = 'vv0'
-- Equation name is 'vv0', location is LC2_B2, type is buried.
vv0 = DFFE(!vv0, GLOBAL( CLK1), VCC, VCC, VCC);
Project Information e:\sz-eda\edap\ceda\led\display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,467K
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