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📄 led.rpt

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-- Node name is 'ledw0' 
-- Equation name is 'ledw0', type is output 
ledw0    =  _LC1_A13;

-- Node name is 'ledw1' 
-- Equation name is 'ledw1', type is output 
ledw1    =  _LC6_A13;

-- Node name is 'ledw2' 
-- Equation name is 'ledw2', type is output 
ledw2    =  _LC8_A13;

-- Node name is 'ledw3' 
-- Equation name is 'ledw3', type is output 
ledw3    =  _LC3_A13;

-- Node name is '|DISPLAY:9|:19' = '|DISPLAY:9|counter0' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = DFFE(!_LC1_A13, GLOBAL( clk2), GLOBAL(!rst),  VCC,  VCC);

-- Node name is '|DISPLAY:9|:18' = '|DISPLAY:9|counter1' 
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = DFFE( _EQ001, GLOBAL( clk2), GLOBAL(!rst),  VCC,  VCC);
  _EQ001 = !_LC1_A13 &  _LC6_A13
         #  _LC1_A13 & !_LC6_A13;

-- Node name is '|DISPLAY:9|:17' = '|DISPLAY:9|counter2' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = DFFE( _EQ002, GLOBAL( clk2), GLOBAL(!rst),  VCC,  VCC);
  _EQ002 = !_LC6_A13 &  _LC8_A13
         # !_LC1_A13 &  _LC8_A13
         #  _LC1_A13 &  _LC6_A13 & !_LC8_A13;

-- Node name is '|DISPLAY:9|:16' = '|DISPLAY:9|counter3' 
-- Equation name is '_LC3_A13', type is buried 
_LC3_A13 = DFFE( _EQ003, GLOBAL( clk2), GLOBAL(!rst),  VCC,  VCC);
  _EQ003 =  _LC3_A13 & !_LC6_A13
         # !_LC1_A13 &  _LC3_A13
         #  _LC3_A13 & !_LC8_A13
         #  _LC1_A13 & !_LC3_A13 &  _LC6_A13 &  _LC8_A13;

-- Node name is '|DISPLAY:9|:27' = '|DISPLAY:9|PAGE0' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = DFFE(!_LC1_A1,  _LC5_A1,  VCC,  VCC,  VCC);

-- Node name is '|DISPLAY:9|:26' = '|DISPLAY:9|PAGE1' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = DFFE( _EQ004,  _LC5_A1,  VCC,  VCC,  VCC);
  _EQ004 =  _LC1_A1 & !_LC2_A1
         # !_LC1_A1 &  _LC2_A1;

-- Node name is '|DISPLAY:9|:25' = '|DISPLAY:9|PAGE2' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = DFFE( _EQ005,  _LC5_A1,  VCC,  VCC,  VCC);
  _EQ005 = !_LC1_A1 &  _LC3_A1
         # !_LC2_A1 &  _LC3_A1
         #  _LC1_A1 &  _LC2_A1 & !_LC3_A1;

-- Node name is '|DISPLAY:9|:24' = '|DISPLAY:9|PAGE3' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = DFFE( _EQ006,  _LC5_A1,  VCC,  VCC,  VCC);
  _EQ006 = !_LC3_A1 &  _LC4_A1
         # !_LC1_A1 &  _LC4_A1
         # !_LC2_A1 &  _LC4_A1
         #  _LC1_A1 &  _LC2_A1 &  _LC3_A1 & !_LC4_A1;

-- Node name is '|DISPLAY:9|:22' = '|DISPLAY:9|vv0' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = DFFE(!_LC5_A1, GLOBAL( clk1),  VCC,  VCC,  VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_A', type is memory 
_EC6_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_A', type is memory 
_EC9_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC7_A', type is memory 
_EC7_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC13_A', type is memory 
_EC13_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_A', type is memory 
_EC4_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC16_A', type is memory 
_EC16_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC3_A', type is memory 
_EC3_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_A', type is memory 
_EC10_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_8' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC5_A', type is memory 
_EC5_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_9' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC15_A', type is memory 
_EC15_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_10' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC2_A', type is memory 
_EC2_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_11' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_A', type is memory 
_EC11_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_12' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_A', type is memory 
_EC8_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_13' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC12_A', type is memory 
_EC12_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_14' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_A', type is memory 
_EC1_A   = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);

-- Node name is '|LPM_ROM:8|altrom:srom|segment0_15' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC14_A', type is memory 
_EC14_A  = MEMORY_SEGMENT( VCC, GLOBAL( clk2), VCC, GND, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, _LC1_A13, _LC6_A13, _LC8_A13, _LC3_A13, _LC1_A1, _LC2_A1, _LC3_A1, _LC4_A1, VCC, VCC, VCC, VCC, VCC, VCC);



Project Information                            e:\sz-eda\edap\ceda\led\led.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 25,918K

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