led.rpt

点阵显示实验示例使用说明 使用模块有：时钟源模块、点阵显示模块

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:      11/144(  7%)     7/ 72(  9%)     0/ 72(  0%)    0/16(  0%)      3/16( 18%)     0/16(  0%)
B:       1/144(  0%)     2/ 72(  2%)     0/ 72(  0%)    0/16(  0%)      2/16( 12%)     0/16(  0%)
C:       3/144(  2%)     3/ 72(  4%)     0/ 72(  0%)    0/16(  0%)      3/16( 18%)     0/16(  0%)
D:       3/144(  2%)     5/ 72(  6%)     0/ 72(  0%)    0/16(  0%)      5/16( 31%)     0/16(  0%)
E:       2/144(  1%)     3/ 72(  4%)     0/ 72(  0%)    0/16(  0%)      3/16( 18%)     0/16(  0%)
F:       4/144(  2%)     4/ 72(  5%)     0/ 72(  0%)    0/16(  0%)      4/16( 25%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      1/24(  4%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
25:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
26:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
27:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
28:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
29:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
30:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
31:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
32:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
33:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
34:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
35:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
36:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:     13/24( 54%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                   e:\sz-eda\edap\ceda\led\led.rpt
led

** CLOCK SIGNALS **

Type     Fan-out       Name
INPUT       20         clk2
DFF          5         |DISPLAY:9|vv0
INPUT        1         clk1


Device-Specific Information:                   e:\sz-eda\edap\ceda\led\led.rpt
led

** CLEAR SIGNALS **

Type     Fan-out       Name
INPUT        4         rst


Device-Specific Information:                   e:\sz-eda\edap\ceda\led\led.rpt
led

** EQUATIONS **

clk1     : INPUT;
clk2     : INPUT;
rst      : INPUT;

-- Node name is 'dout0~fit~in1' 
-- Equation name is 'dout0~fit~in1', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EC6_A);

-- Node name is 'dout0' 
-- Equation name is 'dout0', type is output 
dout0    =  _LC5_B4;

-- Node name is 'dout1~fit~in1' 
-- Equation name is 'dout1~fit~in1', location is LC1_C18, type is buried.
-- synthesized logic cell 
_LC1_C18 = LCELL( _EC9_A);

-- Node name is 'dout1' 
-- Equation name is 'dout1', type is output 
dout1    =  _LC1_C18;

-- Node name is 'dout2~fit~in1' 
-- Equation name is 'dout2~fit~in1', location is LC4_C4, type is buried.
-- synthesized logic cell 
_LC4_C4  = LCELL( _EC7_A);

-- Node name is 'dout2' 
-- Equation name is 'dout2', type is output 
dout2    =  _LC4_C4;

-- Node name is 'dout3~fit~in1' 
-- Equation name is 'dout3~fit~in1', location is LC8_C7, type is buried.
-- synthesized logic cell 
_LC8_C7  = LCELL( _EC13_A);

-- Node name is 'dout3' 
-- Equation name is 'dout3', type is output 
dout3    =  _LC8_C7;

-- Node name is 'dout4~fit~in1' 
-- Equation name is 'dout4~fit~in1', location is LC1_D10, type is buried.
-- synthesized logic cell 
_LC1_D10 = LCELL( _EC4_A);

-- Node name is 'dout4' 
-- Equation name is 'dout4', type is output 
dout4    =  _LC1_D10;

-- Node name is 'dout5~fit~in1' 
-- Equation name is 'dout5~fit~in1', location is LC2_D12, type is buried.
-- synthesized logic cell 
_LC2_D12 = LCELL( _EC16_A);

-- Node name is 'dout5' 
-- Equation name is 'dout5', type is output 
dout5    =  _LC2_D12;

-- Node name is 'dout6~fit~in1' 
-- Equation name is 'dout6~fit~in1', location is LC8_D18, type is buried.
-- synthesized logic cell 
_LC8_D18 = LCELL( _EC3_A);

-- Node name is 'dout6' 
-- Equation name is 'dout6', type is output 
dout6    =  _LC8_D18;

-- Node name is 'dout7~fit~in1' 
-- Equation name is 'dout7~fit~in1', location is LC5_A12, type is buried.
-- synthesized logic cell 
_LC5_A12 = LCELL( _EC10_A);

-- Node name is 'dout7' 
-- Equation name is 'dout7', type is output 
dout7    =  _LC5_A12;

-- Node name is 'dout8~fit~in1' 
-- Equation name is 'dout8~fit~in1', location is LC8_A4, type is buried.
-- synthesized logic cell 
_LC8_A4  = LCELL( _EC5_A);

-- Node name is 'dout8' 
-- Equation name is 'dout8', type is output 
dout8    =  _LC8_A4;

-- Node name is 'dout9~fit~in1' 
-- Equation name is 'dout9~fit~in1', location is LC1_E8, type is buried.
-- synthesized logic cell 
_LC1_E8  = LCELL( _EC15_A);

-- Node name is 'dout9' 
-- Equation name is 'dout9', type is output 
dout9    =  _LC1_E8;

-- Node name is 'dout10~fit~in1' 
-- Equation name is 'dout10~fit~in1', location is LC4_E3, type is buried.
-- synthesized logic cell 
_LC4_E3  = LCELL( _EC2_A);

-- Node name is 'dout10' 
-- Equation name is 'dout10', type is output 
dout10   =  _LC4_E3;

-- Node name is 'dout11~fit~in1' 
-- Equation name is 'dout11~fit~in1', location is LC8_A6, type is buried.
-- synthesized logic cell 
_LC8_A6  = LCELL( _EC11_A);

-- Node name is 'dout11' 
-- Equation name is 'dout11', type is output 
dout11   =  _LC8_A6;

-- Node name is 'dout12~fit~in1' 
-- Equation name is 'dout12~fit~in1', location is LC1_F9, type is buried.
-- synthesized logic cell 
_LC1_F9  = LCELL( _EC8_A);

-- Node name is 'dout12' 
-- Equation name is 'dout12', type is output 
dout12   =  _LC1_F9;

-- Node name is 'dout13~fit~in1' 
-- Equation name is 'dout13~fit~in1', location is LC2_F5, type is buried.
-- synthesized logic cell 
_LC2_F5  = LCELL( _EC12_A);

-- Node name is 'dout13' 
-- Equation name is 'dout13', type is output 
dout13   =  _LC2_F5;

-- Node name is 'dout14~fit~in1' 
-- Equation name is 'dout14~fit~in1', location is LC4_F2, type is buried.
-- synthesized logic cell 
_LC4_F2  = LCELL( _EC1_A);

-- Node name is 'dout14' 
-- Equation name is 'dout14', type is output 
dout14   =  _LC4_F2;

-- Node name is 'dout15~fit~in1' 
-- Equation name is 'dout15~fit~in1', location is LC6_F15, type is buried.
-- synthesized logic cell 
_LC6_F15 = LCELL( _EC14_A);

-- Node name is 'dout15' 
-- Equation name is 'dout15', type is output 
dout15   =  _LC6_F15;