vgacolor.rpt

彩条信号发生器使用说明 使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤： 1. 打开电源+5V 2. 信号连接

  _EQ026 = !_LC3_B25
         # !ll0
         #  ll1
         # !_LC5_B19;

-- Node name is ':824' 
-- Equation name is '_LC2_D25', type is buried 
!_LC2_D25 = _LC2_D25~NOT;
_LC2_D25~NOT = LCELL( _EQ027);
  _EQ027 = !cc1 & !cc2
         # !cc3
         # !cc4;

-- Node name is ':871' 
-- Equation name is '_LC3_B25', type is buried 
!_LC3_B25 = _LC3_B25~NOT;
_LC3_B25~NOT = LCELL( _EQ028);
  _EQ028 =  _LC6_B25
         # !ll8
         # !ll7;

-- Node name is ':1133' 
-- Equation name is '_LC7_D26', type is buried 
_LC7_D26 = LCELL( _EQ029);
  _EQ029 = !cc2
         # !cc1
         # !cc0;

-- Node name is ':1155' 
-- Equation name is '_LC2_D24', type is buried 
_LC2_D24 = LCELL( _EQ030);
  _EQ030 = !cc1 & !cc2
         # !cc3;

-- Node name is ':1182' 
-- Equation name is '_LC3_D25', type is buried 
!_LC3_D25 = _LC3_D25~NOT;
_LC3_D25~NOT = LCELL( _EQ031);
  _EQ031 =  cc1 &  cc2 &  cc3
         #  cc0 &  cc2 &  cc3;

-- Node name is ':1260' 
-- Equation name is '_LC6_D26', type is buried 
_LC6_D26 = LCELL( _EQ032);
  _EQ032 = !cc1 & !cc3
         # !cc0 & !cc3
         # !cc2 & !cc3;

-- Node name is ':1363' 
-- Equation name is '_LC8_D25', type is buried 
_LC8_D25 = LCELL( _EQ033);
  _EQ033 = !_LC3_D25 & !_LC6_D26
         #  cc4 & !_LC6_D26
         # !cc2 & !_LC3_D25
         # !cc2 &  cc4
         # !cc4 & !_LC3_D25;

-- Node name is ':1375' 
-- Equation name is '_LC1_D24', type is buried 
_LC1_D24 = LCELL( _EQ034);
  _EQ034 = !cc4 &  _LC2_D24 &  _LC3_D24
         #  _LC3_D24 &  _LC8_D25;

-- Node name is '~1397~1' 
-- Equation name is '~1397~1', location is LC5_D25, type is buried.
-- synthesized logic cell 
_LC5_D25 = LCELL( _EQ035);
  _EQ035 = !cc2 & !cc3
         # !cc1 & !cc2 & !cc4
         # !cc3 & !cc4;

-- Node name is '~1397~2' 
-- Equation name is '~1397~2', location is LC6_D25, type is buried.
-- synthesized logic cell 
_LC6_D25 = LCELL( _EQ036);
  _EQ036 =  _LC5_D25 & !_LC6_D26
         # !cc4 &  _LC3_D25 & !_LC6_D26
         #  cc4 &  _LC5_D25;

-- Node name is ':1397' 
-- Equation name is '_LC7_D25', type is buried 
_LC7_D25 = LCELL( _EQ037);
  _EQ037 =  _LC6_D25
         # !cc2 & !cc3 & !cc4;

-- Node name is '~1423~1' 
-- Equation name is '~1423~1', location is LC3_D24, type is buried.
-- synthesized logic cell 
_LC3_D24 = LCELL( _EQ038);
  _EQ038 =  cc4
         #  cc3 & !_LC6_D26
         #  cc2 & !_LC6_D26;

-- Node name is ':1423' 
-- Equation name is '_LC4_D25', type is buried 
_LC4_D25 = LCELL( _EQ039);
  _EQ039 =  cc2 &  cc4 &  _LC6_D26
         #  cc3 & !cc4 & !_LC6_D26
         #  cc2 & !cc4 & !_LC6_D26;

-- Node name is ':1435' 
-- Equation name is '_LC1_B28', type is buried 
!_LC1_B28 = _LC1_B28~NOT;
_LC1_B28~NOT = LCELL( _EQ040);
  _EQ040 =  ll8
         #  ll7
         # !_LC5_B28
         #  ll6;

-- Node name is ':1448' 
-- Equation name is '_LC5_B28', type is buried 
!_LC5_B28 = _LC5_B28~NOT;
_LC5_B28~NOT = LCELL( _EQ041);
  _EQ041 =  ll2 &  ll3 &  ll4 &  ll5;

-- Node name is '~1486~1' 
-- Equation name is '~1486~1', location is LC7_B25, type is buried.
-- synthesized logic cell 
_LC7_B25 = LCELL( _EQ042);
  _EQ042 =  ll8
         #  ll7;

-- Node name is ':1486' 
-- Equation name is '_LC5_B25', type is buried 
!_LC5_B25 = _LC5_B25~NOT;
_LC5_B25~NOT = LCELL( _EQ043);
  _EQ043 = !_LC6_B25 &  ll3 &  ll4
         #  _LC7_B25;

-- Node name is ':1537' 
-- Equation name is '_LC2_B28', type is buried 
_LC2_B28 = LCELL( _EQ044);
  _EQ044 =  _LC7_B28 & !ll6 & !ll8
         # !ll7 & !ll8;

-- Node name is ':1550' 
-- Equation name is '_LC7_B28', type is buried 
_LC7_B28 = LCELL( _EQ045);
  _EQ045 = !ll2 & !ll3
         # !ll5
         # !ll4;

-- Node name is ':1588' 
-- Equation name is '_LC2_B25', type is buried 
!_LC2_B25 = _LC2_B25~NOT;
_LC2_B25~NOT = LCELL( _EQ046);
  _EQ046 = !_LC6_B25 &  ll4 &  ll7
         #  ll8;

-- Node name is '~1591~1' 
-- Equation name is '~1591~1', location is LC6_B25, type is buried.
-- synthesized logic cell 
_LC6_B25 = LCELL( _EQ047);
  _EQ047 = !ll5
         # !ll6;

-- Node name is ':1637' 
-- Equation name is '_LC6_B22', type is buried 
_LC6_B22 = LCELL( _EQ048);
  _EQ048 =  _LC3_B28 & !ll6 & !ll7
         # !ll8;

-- Node name is ':1652' 
-- Equation name is '_LC3_B28', type is buried 
_LC3_B28 = LCELL( _EQ049);
  _EQ049 = !ll3 & !ll4
         # !ll2 & !ll4
         # !ll5;

-- Node name is ':1690' 
-- Equation name is '_LC4_B25', type is buried 
!_LC4_B25 = _LC4_B25~NOT;
_LC4_B25~NOT = LCELL( _EQ050);
  _EQ050 = !_LC6_B25 &  ll4
         # !_LC6_B25 &  ll3
         #  ll7;

-- Node name is ':1746' 
-- Equation name is '_LC6_B28', type is buried 
_LC6_B28 = LCELL( _EQ051);
  _EQ051 = !ll5 & !ll6
         #  _LC5_B19 & !ll6;

-- Node name is ':1756' 
-- Equation name is '_LC5_B19', type is buried 
!_LC5_B19 = _LC5_B19~NOT;
_LC5_B19~NOT = LCELL( _EQ052);
  _EQ052 =  ll4
         #  ll3
         #  ll2;

-- Node name is ':1864' 
-- Equation name is '_LC4_B23', type is buried 
_LC4_B23 = LCELL( _EQ053);
  _EQ053 = !_LC2_B25 &  _LC6_B22
         # !_LC2_B25 & !_LC4_B28;

-- Node name is ':1876' 
-- Equation name is '_LC5_B23', type is buried 
_LC5_B23 = LCELL( _EQ054);
  _EQ054 = !_LC1_B28 &  _LC2_B28 & !_LC5_B25
         # !_LC1_B28 &  _LC4_B23 & !_LC5_B25;

-- Node name is '~1892~1' 
-- Equation name is '~1892~1', location is LC8_B25, type is buried.
-- synthesized logic cell 
_LC8_B25 = LCELL( _EQ055);
  _EQ055 =  _LC4_B25 & !_LC6_B22
         #  _LC2_B28;

-- Node name is ':1898' 
-- Equation name is '_LC1_B25', type is buried 
_LC1_B25 = LCELL( _EQ056);
  _EQ056 = !_LC5_B25 &  _LC8_B25
         #  _LC2_B25 & !_LC5_B25
         #  _LC1_B28;

-- Node name is ':1912' 
-- Equation name is '_LC4_B28', type is buried 
_LC4_B28 = LCELL( _EQ057);
  _EQ057 = !_LC4_B25 &  _LC6_B28
         # !_LC4_B25 & !ll7;

-- Node name is ':1924' 
-- Equation name is '_LC1_B23', type is buried 
_LC1_B23 = LCELL( _EQ058);
  _EQ058 = !_LC1_B28 & !_LC5_B25 &  _LC6_B22
         # !_LC1_B28 &  _LC4_B28 & !_LC5_B25;

-- Node name is ':1964' 
-- Equation name is '_LC7_B23', type is buried 
_LC7_B23 = LCELL( _EQ059);
  _EQ059 =  _LC1_D25 & !_LC2_D25 & !_LC3_B25 & !ms1
         # !_LC1_D25 & !_LC2_D25 & !_LC3_B25 &  ms1;

-- Node name is ':1974' 
-- Equation name is '_LC3_B23', type is buried 
_LC3_B23 = LCELL( _EQ060);
  _EQ060 = !_LC2_D25 & !_LC3_B25 &  _LC8_B23 & !ms1
         # !_LC2_D25 & !_LC3_B25 & !_LC8_B23 &  ms1;

-- Node name is ':1984' 
-- Equation name is '_LC6_B23', type is buried 
_LC6_B23 = LCELL( _EQ061);
  _EQ061 =  _LC2_B23 & !_LC2_D25 & !_LC3_B25 & !ms1
         # !_LC2_B23 & !_LC2_D25 & !_LC3_B25 &  ms1;



Project Information                       e:\sz-eda\edap\ceda\vga\vgacolor.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:03
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:06


Memory Allocated
-----------------

Peak memory allocated during compilation  = 33,078K