📄 vgacolor.rpt
字号:
- 4 - D 26 DFFE 0 1 0 5 cc0 (:28)
- 3 - B 22 DFFE 0 4 0 6 ll8 (:30)
- 4 - B 22 DFFE 0 3 0 9 ll7 (:31)
- 1 - B 22 DFFE 0 4 0 6 ll6 (:32)
- 2 - B 22 DFFE 0 4 0 7 ll5 (:33)
- 5 - B 22 DFFE 0 3 0 10 ll4 (:34)
- 3 - B 19 DFFE 0 4 0 7 ll3 (:35)
- 4 - B 19 DFFE 0 4 0 6 ll2 (:36)
- 8 - B 19 DFFE 0 3 0 4 ll1 (:37)
- 7 - B 19 DFFE 0 1 0 5 ll0 (:38)
- 8 - B 23 OR2 0 4 0 1 :233
- 1 - D 25 OR2 0 4 0 1 :245
- 2 - B 23 OR2 0 4 0 1 :257
- 8 - D 26 OR2 ! 0 3 0 2 :410
- 2 - B 19 OR2 ! 0 4 0 8 :576
- 2 - D 25 OR2 ! 0 4 1 3 :824
- 3 - B 25 OR2 ! 0 3 1 4 :871
- 7 - D 26 OR2 0 3 0 3 :1133
- 2 - D 24 OR2 0 3 0 1 :1155
- 3 - D 25 OR2 ! 0 4 0 2 :1182
- 6 - D 26 OR2 0 4 0 4 :1260
- 8 - D 25 OR2 0 4 0 1 :1363
- 1 - D 24 OR2 0 4 0 1 :1375
- 5 - D 25 OR2 s 0 4 0 1 ~1397~1
- 6 - D 25 OR2 s 0 4 0 1 ~1397~2
- 7 - D 25 OR2 0 4 0 1 :1397
- 3 - D 24 OR2 s 0 4 0 1 ~1423~1
- 4 - D 25 OR2 0 4 0 1 :1423
- 1 - B 28 OR2 ! 0 4 0 3 :1435
- 5 - B 28 AND2 ! 0 4 0 1 :1448
- 7 - B 25 OR2 s 0 2 0 1 ~1486~1
- 5 - B 25 OR2 ! 0 4 0 3 :1486
- 2 - B 28 OR2 0 4 0 2 :1537
- 7 - B 28 OR2 0 4 0 1 :1550
- 2 - B 25 OR2 ! 0 4 0 2 :1588
- 6 - B 25 OR2 s 0 2 0 4 ~1591~1
- 6 - B 22 OR2 0 4 0 3 :1637
- 3 - B 28 OR2 0 4 0 1 :1652
- 4 - B 25 OR2 ! 0 4 0 2 :1690
- 6 - B 28 OR2 0 3 0 1 :1746
- 5 - B 19 OR2 ! 0 3 0 2 :1756
- 4 - B 23 OR2 0 3 0 1 :1864
- 5 - B 23 OR2 0 4 0 1 :1876
- 8 - B 25 OR2 s 0 3 0 1 ~1892~1
- 1 - B 25 OR2 0 4 0 1 :1898
- 4 - B 28 OR2 0 3 0 2 :1912
- 1 - B 23 OR2 0 4 0 1 :1924
- 7 - B 23 OR2 1 3 1 0 :1964
- 3 - B 23 OR2 1 3 1 0 :1974
- 6 - B 23 OR2 1 3 1 0 :1984
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\sz-eda\edap\ceda\vga\vgacolor.rpt
vgacolor
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 1/ 72( 1%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 11/144( 7%) 0/ 72( 0%) 21/ 72( 29%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 0/144( 0%) 0/ 72( 0%) 2/ 72( 2%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 3/144( 2%) 0/ 72( 0%) 9/ 72( 12%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\sz-eda\edap\ceda\vga\vgacolor.rpt
vgacolor
** CLOCK SIGNALS **
Type Fan-out Name
DFF 19 cc4
DFF 7 fs2
INPUT 5 ms1
INPUT 4 clk1
Device-Specific Information: e:\sz-eda\edap\ceda\vga\vgacolor.rpt
vgacolor
** EQUATIONS **
clk1 : INPUT;
ms1 : INPUT;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC6_B23;
-- Node name is ':28' = 'cc0'
-- Equation name is 'cc0', location is LC4_D26, type is buried.
cc0 = DFFE(!cc0, fs2, VCC, VCC, VCC);
-- Node name is ':27' = 'cc1'
-- Equation name is 'cc1', location is LC5_D26, type is buried.
cc1 = DFFE( _EQ001, fs2, VCC, VCC, VCC);
_EQ001 = !cc0 & cc1 & !_LC8_D26
# cc0 & !cc1 & !_LC8_D26;
-- Node name is ':26' = 'cc2'
-- Equation name is 'cc2', location is LC1_D26, type is buried.
cc2 = DFFE( _EQ002, fs2, VCC, VCC, VCC);
_EQ002 = !cc1 & cc2 & !_LC8_D26
# !cc0 & cc2 & !_LC8_D26
# cc0 & cc1 & !cc2 & !_LC8_D26;
-- Node name is ':25' = 'cc3'
-- Equation name is 'cc3', location is LC3_D26, type is buried.
cc3 = DFFE( _EQ003, fs2, VCC, VCC, VCC);
_EQ003 = cc3 & _LC7_D26
# !cc3 & !_LC7_D26;
-- Node name is ':24' = 'cc4'
-- Equation name is 'cc4', location is LC2_D26, type is buried.
cc4 = DFFE( _EQ004, fs2, VCC, VCC, VCC);
_EQ004 = !cc3 & cc4
# cc4 & _LC7_D26
# cc3 & !cc4 & !_LC7_D26;
-- Node name is ':22' = 'fs0'
-- Equation name is 'fs0', location is LC3_D36, type is buried.
fs0 = DFFE(!fs0, GLOBAL( clk1), VCC, VCC, VCC);
-- Node name is ':21' = 'fs1'
-- Equation name is 'fs1', location is LC2_D36, type is buried.
fs1 = DFFE( _EQ005, GLOBAL( clk1), VCC, VCC, VCC);
_EQ005 = fs0 & !fs1
# !fs0 & fs1;
-- Node name is ':20' = 'fs2'
-- Equation name is 'fs2', location is LC1_D36, type is buried.
fs2 = DFFE( _EQ006, GLOBAL( clk1), VCC, VCC, VCC);
_EQ006 = !fs1 & fs2
# !fs0 & fs2
# fs0 & fs1 & !fs2 & !fs3;
-- Node name is ':19' = 'fs3'
-- Equation name is 'fs3', location is LC4_D36, type is buried.
fs3 = DFFE( _EQ007, GLOBAL( clk1), VCC, VCC, VCC);
_EQ007 = !fs1 & fs3
# !fs0 & fs3
# fs0 & fs1 & fs2 & !fs3;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC3_B23;
-- Node name is 'hs'
-- Equation name is 'hs', type is output
hs = !_LC2_D25;
-- Node name is ':38' = 'll0'
-- Equation name is 'll0', location is LC7_B19, type is buried.
ll0 = DFFE(!ll0, cc4, VCC, VCC, VCC);
-- Node name is ':37' = 'll1'
-- Equation name is 'll1', location is LC8_B19, type is buried.
ll1 = DFFE( _EQ008, cc4, VCC, VCC, VCC);
_EQ008 = !_LC2_B19 & ll0 & !ll1
# !_LC2_B19 & !ll0 & ll1;
-- Node name is ':36' = 'll2'
-- Equation name is 'll2', location is LC4_B19, type is buried.
ll2 = DFFE( _EQ009, cc4, VCC, VCC, VCC);
_EQ009 = !_LC2_B19 & !ll0 & ll2
# !_LC2_B19 & !ll1 & ll2
# !_LC2_B19 & ll0 & ll1 & !ll2;
-- Node name is ':35' = 'll3'
-- Equation name is 'll3', location is LC3_B19, type is buried.
ll3 = DFFE( _EQ010, cc4, VCC, VCC, VCC);
_EQ010 = !_LC2_B19 & !_LC6_B19 & ll3
# !_LC2_B19 & !ll2 & ll3
# !_LC2_B19 & _LC6_B19 & ll2 & !ll3;
-- Node name is ':34' = 'll4'
-- Equation name is 'll4', location is LC5_B22, type is buried.
ll4 = DFFE( _EQ011, cc4, VCC, VCC, VCC);
_EQ011 = !_LC1_B19 & !_LC2_B19 & ll4
# _LC1_B19 & !_LC2_B19 & !ll4;
-- Node name is ':33' = 'll5'
-- Equation name is 'll5', location is LC2_B22, type is buried.
ll5 = DFFE( _EQ012, cc4, VCC, VCC, VCC);
_EQ012 = !_LC2_B19 & !ll4 & ll5
# !_LC1_B19 & !_LC2_B19 & ll5
# _LC1_B19 & !_LC2_B19 & ll4 & !ll5;
-- Node name is ':32' = 'll6'
-- Equation name is 'll6', location is LC1_B22, type is buried.
ll6 = DFFE( _EQ013, cc4, VCC, VCC, VCC);
_EQ013 = !_LC2_B19 & !ll5 & ll6
# !_LC2_B19 & !_LC7_B22 & ll6
# !_LC2_B19 & _LC7_B22 & ll5 & !ll6;
-- Node name is ':31' = 'll7'
-- Equation name is 'll7', location is LC4_B22, type is buried.
ll7 = DFFE( _EQ014, cc4, VCC, VCC, VCC);
_EQ014 = !_LC2_B19 & !_LC8_B22 & ll7
# !_LC2_B19 & _LC8_B22 & !ll7;
-- Node name is ':30' = 'll8'
-- Equation name is 'll8', location is LC3_B22, type is buried.
ll8 = DFFE( _EQ015, cc4, VCC, VCC, VCC);
_EQ015 = !_LC2_B19 & !ll7 & ll8
# !_LC2_B19 & !_LC8_B22 & ll8
# !_LC2_B19 & _LC8_B22 & ll7 & !ll8;
-- Node name is ':9' = 'mode0'
-- Equation name is 'mode0', location is LC4_D33, type is buried.
mode0 = DFFE( _EQ016, GLOBAL( ms1), VCC, VCC, VCC);
_EQ016 = !mode0 & !mode1;
-- Node name is ':8' = 'mode1'
-- Equation name is 'mode1', location is LC1_D33, type is buried.
mode1 = DFFE( _EQ017, GLOBAL( ms1), VCC, VCC, VCC);
_EQ017 = mode0 & !mode1;
-- Node name is 'r'
-- Equation name is 'r', type is output
r = _LC7_B23;
-- Node name is 'vs'
-- Equation name is 'vs', type is output
vs = !_LC3_B25;
-- Node name is '|LPM_ADD_SUB:631|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = LCELL( _EQ018);
_EQ018 = ll0 & ll1;
-- Node name is '|LPM_ADD_SUB:631|addcore:adder|:83' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B19', type is buried
_LC1_B19 = LCELL( _EQ019);
_EQ019 = ll0 & ll1 & ll2 & ll3;
-- Node name is '|LPM_ADD_SUB:631|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = LCELL( _EQ020);
_EQ020 = _LC1_B19 & ll4;
-- Node name is '|LPM_ADD_SUB:631|addcore:adder|:95' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B22', type is buried
_LC8_B22 = LCELL( _EQ021);
_EQ021 = _LC1_B19 & ll4 & ll5 & ll6;
-- Node name is ':233'
-- Equation name is '_LC8_B23', type is buried
_LC8_B23 = LCELL( _EQ022);
_EQ022 = !_LC1_D24 & _LC5_B23 & !mode0 & mode1
# _LC1_D24 & !_LC5_B23 & !mode0
# _LC5_B23 & mode0 & !mode1
# _LC1_D24 & !mode0 & !mode1;
-- Node name is ':245'
-- Equation name is '_LC1_D25', type is buried
_LC1_D25 = LCELL( _EQ023);
_EQ023 = _LC1_B25 & mode0 & !mode1
# _LC1_B25 & !_LC7_D25 & !mode0 & mode1
# !_LC1_B25 & _LC7_D25 & !mode0
# _LC7_D25 & !mode0 & !mode1;
-- Node name is ':257'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ024);
_EQ024 = _LC1_B23 & mode0 & !mode1
# _LC1_B23 & !_LC4_D25 & !mode0 & mode1
# !_LC1_B23 & _LC4_D25 & !mode0
# _LC4_D25 & !mode0 & !mode1;
-- Node name is ':410'
-- Equation name is '_LC8_D26', type is buried
!_LC8_D26 = _LC8_D26~NOT;
_LC8_D26~NOT = LCELL( _EQ025);
_EQ025 = !cc4
# !cc3
# _LC7_D26;
-- Node name is ':576'
-- Equation name is '_LC2_B19', type is buried
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ026);
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