📄 reset.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity reset is
port(
clk:in std_logic;
key: in std_logic;
cpo: out std_logic);
end reset ;
architecture behavor of reset is
signal cp:std_logic;
signal jsp:integer range 0 to 5;
begin
process(clk)
begin
if(clk'event and clk='1')then
if(key='1') then
if jsp=5 then
jsp<=jsp;
else
jsp<=jsp+1;
end if;
end if;
if (jsp>=4 and key='0' ) then
cp<='1';jsp<=0;
else
cp<='0';
end if;
end if;
cpo<=cp;
end process;
end behavor;
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