fengpin.rpt
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RPT
464 行
Device-Specific Information: f:\display\fengpin.rpt
fengpin
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 121 H TFFE + t 0 0 0 0 9 1 0 b9 (:4)
- 116 H TFFE + t 0 0 0 0 8 1 1 b8 (:5)
(73) 115 H TFFE + t 0 0 0 0 7 1 2 b7 (:6)
- 114 H TFFE + t 0 0 0 0 6 1 3 b6 (:7)
- 113 H TFFE + t 0 0 0 0 5 1 4 b5 (:8)
- 122 H TFFE + t 0 0 0 0 4 1 5 b4 (:9)
(74) 117 H TFFE + t 0 0 0 0 3 1 6 b3 (:10)
(75) 118 H TFFE + t 0 0 0 0 2 1 7 b2 (:11)
- 119 H TFFE + t 0 0 0 0 1 1 8 b1 (:12)
(76) 120 H TFFE + t 0 0 0 0 0 1 9 b0 (:13)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\display\fengpin.rpt
fengpin
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+--------------------- LC123 fpclk
| +------------------- LC121 b9
| | +----------------- LC116 b8
| | | +--------------- LC115 b7
| | | | +------------- LC114 b6
| | | | | +----------- LC113 b5
| | | | | | +--------- LC122 b4
| | | | | | | +------- LC117 b3
| | | | | | | | +----- LC118 b2
| | | | | | | | | +--- LC119 b1
| | | | | | | | | | +- LC120 b0
| | | | | | | | | | |
| | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC121-> * * - - - - - - - - - | - - - - - - - * | <-- b9
LC116-> * * * - - - - - - - - | - - - - - - - * | <-- b8
LC115-> * * * * - - - - - - - | - - - - - - - * | <-- b7
LC114-> * * * * * - - - - - - | - - - - - - - * | <-- b6
LC113-> * * * * * * - - - - - | - - - - - - - * | <-- b5
LC122-> * * * * * * * - - - - | - - - - - - - * | <-- b4
LC117-> * * * * * * * * - - - | - - - - - - - * | <-- b3
LC118-> * * * * * * * * * - - | - - - - - - - * | <-- b2
LC119-> * * * * * * * * * * - | - - - - - - - * | <-- b1
LC120-> * * * * * * * * * * * | - - - - - - - * | <-- b0
Pin
83 -> - - - - - - - - - - - | - - - - - - - - | <-- clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\display\fengpin.rpt
fengpin
** EQUATIONS **
clk : INPUT;
-- Node name is ':13' = 'b0'
-- Equation name is 'b0', location is LC120, type is buried.
b0 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':12' = 'b1'
-- Equation name is 'b1', location is LC119, type is buried.
b1 = TFFE( b0, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':11' = 'b2'
-- Equation name is 'b2', location is LC118, type is buried.
b2 = TFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = b0 & b1;
-- Node name is ':10' = 'b3'
-- Equation name is 'b3', location is LC117, type is buried.
b3 = TFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = b0 & b1 & b2;
-- Node name is ':9' = 'b4'
-- Equation name is 'b4', location is LC122, type is buried.
b4 = TFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = b0 & b1 & b2 & b3;
-- Node name is ':8' = 'b5'
-- Equation name is 'b5', location is LC113, type is buried.
b5 = TFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = b0 & b1 & b2 & b3 & b4;
-- Node name is ':7' = 'b6'
-- Equation name is 'b6', location is LC114, type is buried.
b6 = TFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = b0 & b1 & b2 & b3 & b4 & b5;
-- Node name is ':6' = 'b7'
-- Equation name is 'b7', location is LC115, type is buried.
b7 = TFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = b0 & b1 & b2 & b3 & b4 & b5 & b6;
-- Node name is ':5' = 'b8'
-- Equation name is 'b8', location is LC116, type is buried.
b8 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7;
-- Node name is ':4' = 'b9'
-- Equation name is 'b9', location is LC121, type is buried.
b9 = TFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8;
-- Node name is 'fpclk' = 'b10'
-- Equation name is 'fpclk', location is LC123, type is output.
fpclk = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = b0 & b1 & b2 & b3 & b4 & b5 & b6 & b7 & b8 & b9;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\display\fengpin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:02
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,589K
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