dianzhen.rpt
来自「此为用VHDL编写的可实现动感图像的点阵」· RPT 代码 · 共 1,167 行 · 第 1/5 页
RPT
1,167 行
B: LC17 - LC32 16/16(100%) 1/ 8( 12%) 16/16(100%) 21/36( 58%)
C: LC33 - LC48 16/16(100%) 1/ 8( 12%) 13/16( 81%) 16/36( 44%)
D: LC49 - LC64 16/16(100%) 1/ 8( 12%) 16/16(100%) 29/36( 80%)
E: LC65 - LC80 16/16(100%) 1/ 8( 12%) 0/16( 0%) 18/36( 50%)
F: LC81 - LC96 16/16(100%) 8/ 8(100%) 0/16( 0%) 21/36( 58%)
G: LC97 - LC112 14/16( 87%) 8/ 8(100%) 9/16( 56%) 27/36( 75%)
H: LC113 - LC128 16/16(100%) 0/ 8( 0%) 1/16( 6%) 17/36( 47%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 23/64 ( 35%)
Total logic cells used: 126/128 ( 98%)
Total shareable expanders used: 22/128 ( 17%)
Total Turbo logic cells used: 126/128 ( 98%)
Total shareable expanders not available (n/a): 48/128 ( 37%)
Average fan-in: 7.87
Total fan-in: 992
Total input pins required: 4
Total fast input logic cells required: 0
Total output pins required: 16
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 126
Total flipflops required: 72
Total product terms required: 477
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 22
Synthesized logic cells: 47/ 128 ( 36%)
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 clk
12 (3) (A) INPUT 0 0 0 0 0 0 4 manualkey
10 (6) (A) INPUT 0 0 0 0 0 0 4 resetkey
11 (5) (A) INPUT 0 0 0 0 0 0 4 selectkey
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
58 91 F FF t 0 0 0 0 2 0 0 H1
60 93 F FF t 0 0 0 0 2 0 0 H2
57 88 F FF t 0 0 0 0 2 0 0 H3
61 94 F FF t 0 0 0 0 2 0 0 H4
56 86 F FF t 0 0 0 0 2 0 0 H5
55 85 F FF t 0 0 0 0 2 0 0 H6
54 83 F FF t 0 0 0 0 2 0 0 H7
45 67 E FF t 0 0 0 0 2 0 0 H8
65 101 G FF t 0 0 0 0 2 0 0 L1
64 99 G FF t 0 0 0 0 2 0 0 L2
41 49 D FF t 0 0 0 0 2 0 0 L3
67 104 G FF t 0 0 0 0 2 0 0 L4
68 105 G FF t 0 0 0 0 2 0 0 L5
69 107 G FF t 0 0 0 0 2 0 0 L6
70 109 G FF t 0 0 0 0 2 0 0 L7
63 97 G FF t 0 0 0 0 2 0 0 L8
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 116 H TFFE + t 0 0 0 0 10 16 41 |FENGPIN:72|b10 (|FENGPIN:72|:3)
(77) 123 H TFFE + t 0 0 0 0 9 0 1 |FENGPIN:72|b9 (|FENGPIN:72|:4)
(74) 117 H TFFE + t 0 0 0 0 8 0 2 |FENGPIN:72|b8 (|FENGPIN:72|:5)
- 121 H TFFE + t 0 0 0 0 7 0 3 |FENGPIN:72|b7 (|FENGPIN:72|:6)
- 124 H TFFE + t 0 0 0 0 6 0 4 |FENGPIN:72|b6 (|FENGPIN:72|:7)
(79) 125 H TFFE + t 0 0 0 0 5 0 5 |FENGPIN:72|b5 (|FENGPIN:72|:8)
(81) 128 H TFFE + t 0 0 0 0 4 0 6 |FENGPIN:72|b4 (|FENGPIN:72|:9)
- 127 H TFFE + t 0 0 0 0 3 0 7 |FENGPIN:72|b3 (|FENGPIN:72|:10)
(80) 126 H TFFE + t 0 0 0 0 2 0 8 |FENGPIN:72|b2 (|FENGPIN:72|:11)
(76) 120 H TFFE + t 0 0 0 0 1 0 9 |FENGPIN:72|b1 (|FENGPIN:72|:12)
- 119 H TFFE + t 0 0 0 0 0 0 10 |FENGPIN:72|b0 (|FENGPIN:72|:13)
- 62 D DFFE t 0 0 0 1 4 0 4 |MANUALSWITCH:64|jsp2 (|MANUALSWITCH:64|:5)
(35) 59 D DFFE t 0 0 0 1 4 0 3 |MANUALSWITCH:64|jsp1 (|MANUALSWITCH:64|:6)
(34) 61 D DFFE t 0 0 0 1 4 0 3 |MANUALSWITCH:64|jsp0 (|MANUALSWITCH:64|:7)
(39) 53 D DFFE t 0 0 0 1 2 0 2 |MANUALSWITCH:64|cp (|MANUALSWITCH:64|:8)
- 82 F TFFE t 0 0 0 0 2 0 7 |MANUALSWITCH:64|count1 (|MANUALSWITCH:64|:9)
(21) 19 B TFFE t 0 0 0 0 1 0 8 |MANUALSWITCH:64|count0 (|MANUALSWITCH:64|:10)
(51) 77 E TFFE t 0 0 0 0 15 0 56 |MANUAL:81|b12 (|MANUAL:81|:39)
- 68 E TFFE t 0 0 0 0 14 0 57 |MANUAL:81|b11 (|MANUAL:81|:40)
- 79 E TFFE t 0 0 0 0 13 0 58 |MANUAL:81|b10 (|MANUAL:81|:41)
- 78 E TFFE t 0 0 0 0 12 0 59 |MANUAL:81|b9 (|MANUAL:81|:42)
- 76 E TFFE t 0 0 0 0 11 0 67 |MANUAL:81|b8 (|MANUAL:81|:43)
- 66 E TFFE t 0 0 0 0 10 0 14 |MANUAL:81|b7 (|MANUAL:81|:44)
(44) 65 E TFFE t 0 0 0 0 9 0 15 |MANUAL:81|b6 (|MANUAL:81|:45)
(48) 72 E TFFE t 0 0 0 0 8 0 8 |MANUAL:81|b5 (|MANUAL:81|:46)
(75) 118 H TFFE t 0 0 0 0 7 0 9 |MANUAL:81|b4 (|MANUAL:81|:47)
- 122 H DFFE t 1 0 1 0 6 0 10 |MANUAL:81|b3 (|MANUAL:81|:48)
(73) 115 H DFFE t 0 0 0 0 5 0 77 |MANUAL:81|b2 (|MANUAL:81|:49)
- 113 H DFFE t 0 0 0 0 4 0 78 |MANUAL:81|b1 (|MANUAL:81|:50)
- 114 H DFFE t 0 0 0 0 3 0 78 |MANUAL:81|b0 (|MANUAL:81|:51)
- 58 D DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c0 (|MANUAL:81|:58)
(52) 80 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c1 (|MANUAL:81|:59)
- 71 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c2 (|MANUAL:81|:60)
(49) 73 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c3 (|MANUAL:81|:61)
(50) 75 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c4 (|MANUAL:81|:62)
(46) 69 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c5 (|MANUAL:81|:63)
- 70 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c6 (|MANUAL:81|:64)
- 74 E DFFE t 0 0 0 0 9 1 0 |MANUAL:81|c7 (|MANUAL:81|:65)
(37) 56 D DFFE t 6 0 1 0 14 1 0 |MANUAL:81|d0 (|MANUAL:81|:79)
- 55 D DFFE t 1 0 1 0 13 1 0 |MANUAL:81|d1 (|MANUAL:81|:80)
- 87 F DFFE t 0 0 0 0 3 1 0 |MANUAL:81|d2 (|MANUAL:81|:81)
- 92 F DFFE t 0 0 0 0 3 1 0 |MANUAL:81|d3 (|MANUAL:81|:82)
- 95 F DFFE t 0 0 0 0 3 1 0 |MANUAL:81|d4 (|MANUAL:81|:83)
(62) 96 F DFFE t 0 0 0 0 3 1 0 |MANUAL:81|d5 (|MANUAL:81|:84)
- 100 G DFFE t 4 0 0 0 13 1 0 |MANUAL:81|d6 (|MANUAL:81|:85)
- 111 G DFFE t 1 0 1 0 12 1 0 |MANUAL:81|d7 (|MANUAL:81|:86)
(27) 43 C OR2 s t 0 0 0 0 10 0 1 |MANUAL:81|~22344~1
(18) 24 B OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22344~2
(25) 45 C OR2 s t 0 0 0 0 10 0 1 |MANUAL:81|~22344~3
- 54 D OR2 s t 1 0 1 0 12 0 1 |MANUAL:81|~22344~4
- 28 B OR2 s t 0 0 0 0 11 0 1 |MANUAL:81|~22344~5
(24) 46 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22359~1
- 7 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22359~2
- 63 D OR2 s t 1 0 1 0 13 0 1 |MANUAL:81|~22359~3
(14) 32 B OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22359~4
- 9 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22359~5
- 47 C OR2 s t 0 0 0 0 10 0 1 |MANUAL:81|~22359~6
(33) 64 D OR2 t 0 0 0 0 7 0 1 |MANUAL:81|:22375
(23) 48 C OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22376~1
- 31 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22376~2
(16) 27 B OR2 s t 1 0 1 0 8 0 1 |MANUAL:81|~22376~3
(20) 21 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22376~4
- 22 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22376~5
- 4 A OR2 s t 2 0 1 0 14 0 1 |MANUAL:81|~22376~6
(71) 112 G AND2 t 4 0 0 0 12 0 1 |MANUAL:81|:22376
(28) 40 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22391~1
- 23 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22391~2
(29) 38 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22391~3
(15) 29 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22391~4
- 30 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22391~5
- 39 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22391~6
(30) 37 C AND2 t ! 2 0 1 0 16 0 1 |MANUAL:81|:22391
- 52 D OR2 t 2 0 1 0 7 0 2 |MANUAL:81|:22405
(31) 35 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22406~1
- 34 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22406~2
(36) 57 D OR2 s t 2 0 1 0 12 0 1 |MANUAL:81|~22406~3
- 26 B OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22406~4
(5) 14 A OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22406~5
(6) 13 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22406~6
- 10 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22406~7
(9) 8 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22406~8
(17) 25 B AND2 t 0 0 0 0 11 0 1 |MANUAL:81|:22406
- 60 D OR2 t 2 0 1 0 7 0 1 |MANUAL:81|:22420
- 41 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22421~1
- 44 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22421~2
- 42 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22421~3
(22) 17 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22421~4
- 18 B OR2 s t 1 0 1 0 9 0 1 |MANUAL:81|~22421~5
- 20 B AND2 t 4 0 0 0 15 0 1 |MANUAL:81|:22421
(40) 51 D OR2 s t 0 0 0 0 12 0 1 |MANUAL:81|~22434~1
- 1 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22434~2
(12) 3 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22434~3
(11) 5 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22434~4
- 2 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22434~5
- 36 C OR2 s t 0 0 0 0 10 0 1 |MANUAL:81|~22434~6
- 33 C OR2 s t 1 0 1 0 10 0 1 |MANUAL:81|~22449~1
- 50 D OR2 s t 1 0 1 0 13 0 1 |MANUAL:81|~22449~2
(4) 16 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22449~3
- 15 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22449~4
- 12 A OR2 s t 1 0 1 0 11 0 1 |MANUAL:81|~22449~5
- 110 G DFFE t 0 0 0 1 4 0 4 |RESET:73|jsp2 (|RESET:73|:4)
- 106 G DFFE t 0 0 0 1 4 0 3 |RESET:73|jsp1 (|RESET:73|:5)
- 98 G DFFE t 0 0 0 1 4 0 3 |RESET:73|jsp0 (|RESET:73|:6)
- 102 G DFFE t 0 0 0 1 2 0 13 |RESET:73|cp (|RESET:73|:7)
- 90 F DFFE t 0 0 0 1 4 0 4 |SELECTSWITCH:44|jsp2 (|SELECTSWITCH:44|:5)
- 89 F DFFE t 0 0 0 1 4 0 3 |SELECTSWITCH:44|jsp1 (|SELECTSWITCH:44|:6)
- 84 F DFFE t 0 0 0 1 4 0 3 |SELECTSWITCH:44|jsp0 (|SELECTSWITCH:44|:7)
- 81 F DFFE t 0 0 0 1 2 0 2 |SELECTSWITCH:44|cp (|SELECTSWITCH:44|:8)
(8) 11 A TFFE t 0 0 0 0 2 0 66 |SELECTSWITCH:44|count1 (|SELECTSWITCH:44|:9)
(10) 6 A TFFE t 0 0 0 0 1 0 57 |SELECTSWITCH:44|count0 (|SELECTSWITCH:44|:10)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
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