📄 dianzhen.rpt
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Project Information d:\display\dianzhen.rpt
MAX+plus II Compiler Report File
Version 10.1 06/12/2001
Compiled: 09/23/2004 20:50:14
Copyright (C) 1988-2001 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
dianzhen EPM7128SLC84-6 4 16 0 126 22 98 %
User Pins: 4 16 0
Project Information d:\display\dianzhen.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\display\dianzhen.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
dianzhen@83 clk
dianzhen@58 H1
dianzhen@60 H2
dianzhen@57 H3
dianzhen@61 H4
dianzhen@56 H5
dianzhen@55 H6
dianzhen@54 H7
dianzhen@45 H8
dianzhen@65 L1
dianzhen@64 L2
dianzhen@41 L3
dianzhen@67 L4
dianzhen@68 L5
dianzhen@69 L6
dianzhen@70 L7
dianzhen@63 L8
dianzhen@12 manualkey
dianzhen@10 resetkey
dianzhen@11 selectkey
Project Information d:\display\dianzhen.rpt
** FILE HIERARCHY **
|selectswitch:44|
|selectswitch:44|lpm_add_sub:68|
|selectswitch:44|lpm_add_sub:68|addcore:adder|
|selectswitch:44|lpm_add_sub:68|addcore:adder|addcore:adder0|
|selectswitch:44|lpm_add_sub:68|altshift:result_ext_latency_ffs|
|selectswitch:44|lpm_add_sub:68|altshift:carry_ext_latency_ffs|
|selectswitch:44|lpm_add_sub:68|altshift:oflow_ext_latency_ffs|
|selectswitch:44|lpm_add_sub:242|
|selectswitch:44|lpm_add_sub:242|addcore:adder|
|selectswitch:44|lpm_add_sub:242|addcore:adder|addcore:adder0|
|selectswitch:44|lpm_add_sub:242|altshift:result_ext_latency_ffs|
|selectswitch:44|lpm_add_sub:242|altshift:carry_ext_latency_ffs|
|selectswitch:44|lpm_add_sub:242|altshift:oflow_ext_latency_ffs|
|manualswitch:64|
|manualswitch:64|lpm_add_sub:68|
|manualswitch:64|lpm_add_sub:68|addcore:adder|
|manualswitch:64|lpm_add_sub:68|addcore:adder|addcore:adder0|
|manualswitch:64|lpm_add_sub:68|altshift:result_ext_latency_ffs|
|manualswitch:64|lpm_add_sub:68|altshift:carry_ext_latency_ffs|
|manualswitch:64|lpm_add_sub:68|altshift:oflow_ext_latency_ffs|
|manualswitch:64|lpm_add_sub:242|
|manualswitch:64|lpm_add_sub:242|addcore:adder|
|manualswitch:64|lpm_add_sub:242|addcore:adder|addcore:adder0|
|manualswitch:64|lpm_add_sub:242|altshift:result_ext_latency_ffs|
|manualswitch:64|lpm_add_sub:242|altshift:carry_ext_latency_ffs|
|manualswitch:64|lpm_add_sub:242|altshift:oflow_ext_latency_ffs|
|fengpin:72|
|fengpin:72|lpm_add_sub:59|
|fengpin:72|lpm_add_sub:59|addcore:adder|
|fengpin:72|lpm_add_sub:59|addcore:adder|addcore:adder1|
|fengpin:72|lpm_add_sub:59|addcore:adder|addcore:adder0|
|fengpin:72|lpm_add_sub:59|altshift:result_ext_latency_ffs|
|fengpin:72|lpm_add_sub:59|altshift:carry_ext_latency_ffs|
|fengpin:72|lpm_add_sub:59|altshift:oflow_ext_latency_ffs|
|reset:73|
|reset:73|lpm_add_sub:66|
|reset:73|lpm_add_sub:66|addcore:adder|
|reset:73|lpm_add_sub:66|addcore:adder|addcore:adder0|
|reset:73|lpm_add_sub:66|altshift:result_ext_latency_ffs|
|reset:73|lpm_add_sub:66|altshift:carry_ext_latency_ffs|
|reset:73|lpm_add_sub:66|altshift:oflow_ext_latency_ffs|
|manual:81|
|manual:81|lpm_add_sub:156|
|manual:81|lpm_add_sub:156|addcore:adder|
|manual:81|lpm_add_sub:156|addcore:adder|addcore:adder1|
|manual:81|lpm_add_sub:156|addcore:adder|addcore:adder0|
|manual:81|lpm_add_sub:156|altshift:result_ext_latency_ffs|
|manual:81|lpm_add_sub:156|altshift:carry_ext_latency_ffs|
|manual:81|lpm_add_sub:156|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
***** Logic for device 'dianzhen' compiled without errors.
Device: EPM7128SLC84-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
MultiVolt I/O = OFF
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** ERROR SUMMARY **
Info: Chip 'dianzhen' in device 'EPM7128SLC84-6' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
s
e r R R R R R R R R R R R
l e E E E E E E E E E E E
e s S S S S S V S S S S S S
c e E E E E E C E E E V E E E
t t R R R R R C R R R C R R R
k k V V G V V V I G G G c G V V V C V V V
e e E E N E E E N N N N l N E E E I E E E
y y D D D D D D T D D D k D D D D O D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
manualkey | 12 74 | RESERVED
VCCIO | 13 73 | RESERVED
#TDI | 14 72 | GND
RESERVED | 15 71 | #TDO
RESERVED | 16 70 | L7
RESERVED | 17 69 | L6
RESERVED | 18 68 | L5
GND | 19 67 | L4
RESERVED | 20 66 | VCCIO
RESERVED | 21 65 | L1
RESERVED | 22 EPM7128SLC84-6 64 | L2
#TMS | 23 63 | L8
RESERVED | 24 62 | #TCK
RESERVED | 25 61 | H4
VCCIO | 26 60 | H2
RESERVED | 27 59 | GND
RESERVED | 28 58 | H1
RESERVED | 29 57 | H3
RESERVED | 30 56 | H5
RESERVED | 31 55 | H6
GND | 32 54 | H7
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
R R R R R V R R L G V R H R G R R R R R V
E E E E E C E E 3 N C E 8 E N E E E E E C
S S S S S C S S D C S S D S S S S S C
E E E E E I E E I E E E E E E E I
R R R R R O R R N R R R R R R R O
V V V V V V V T V V V V V V V
E E E E E E E E E E E E E E
D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\display\dianzhen.rpt
dianzhen
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 16/16(100%) 3/ 8( 37%) 15/16( 93%) 28/36( 77%)
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