📄 div.rpt
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| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC32 -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2
LC31 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gs2
LC17 -> - - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node2
LC18 -> - - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node3
LC19 -> - - - - - - - - - - - - - * - - | * * | <-- |LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node2
LC21 -> - - - - - - - - - - - - - * - - | * * | <-- |LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node3
LC22 -> - - - - - - - - - - - - - * - - | * * | <-- |LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node4
LC23 -> - - - - - - - - - - - - - * - - | * * | <-- |LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node5
LC24 -> - - - - - - - - - - - - - * * - | * * | <-- ~316~1
Pin
4 -> - - - - - * - - - - - - - * * - | * * | <-- A0
9 -> - * - - - * - * * - - - - * - * | * * | <-- A1
8 -> - * * - - * * * * * * * * * * * | * * | <-- A2
11 -> - - - * - - - - - - - - - - - - | - * | <-- A3
7 -> * * * * * * * * * * * * * * * * | * * | <-- B0
6 -> * * * * * * * * * - * * * * * * | * * | <-- B1
5 -> * * * * * * * - * - - * * * * * | * * | <-- B2
12 -> - - - * - - - - - - - - - - - - | - * | <-- B3
LC4 -> - - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node1
LC1 -> - - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node4
LC2 -> - - - - - - - - - - - - - * * - | * * | <-- |LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node5
LC8 -> * - - - - - - - - - - - - - - - | - * | <-- ~171~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\divi\div.rpt
div
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A3 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
B3 : INPUT;
-- Node name is 'C0'
-- Equation name is 'C0', location is LC026, type is output.
C0 = LCELL( _EQ001 $ GND);
_EQ001 = !_LC008 & _X001;
_X001 = EXP(!B0 & !B1 & !B2);
-- Node name is 'C1'
-- Equation name is 'C1', location is LC027, type is output.
C1 = LCELL( _EQ002 $ GND);
_EQ002 = A1 & A2 & B1 & !B2
# A1 & B0 & !B1 & !B2
# A2 & !B0 & B1 & !B2;
-- Node name is 'C2'
-- Equation name is 'C2', location is LC028, type is output.
C2 = LCELL( _EQ003 $ GND);
_EQ003 = A2 & B0 & !B1 & !B2;
-- Node name is 'C3'
-- Equation name is 'C3', location is LC030, type is output.
C3 = LCELL( _EQ004 $ VCC);
_EQ004 = !B0 & !B1 & !B2
# A3 & B3
# !A3 & !B3;
-- Node name is 'DIVz'
-- Equation name is 'DIVz', location is LC020, type is output.
DIVz = LCELL( _EQ005 $ GND);
_EQ005 = !B0 & !B1 & !B2;
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( _EQ006 $ GND);
_EQ006 = A2 & !B1 & B2
# A2 & !B0 & !B1
# A1 & !B0 & _X002
# A0 & _X002 & _X003;
_X002 = EXP(!A2 & B1);
_X003 = EXP(!A1 & B0);
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|gs2' from file "addcore.tdf" line 148, column 7
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( _EQ007 $ GND);
_EQ007 = A2 & !B0 & !B1 & !B2
# A2 & !B1 & B2;
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( _EQ008 $ _EQ009);
_EQ008 = A1 & !B0 & _X003;
_X003 = EXP(!A1 & B0);
_EQ009 = !A1 & B0;
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( _EQ010 $ _EQ011);
_EQ010 = A1 & !B0
# _X003;
_X003 = EXP(!A1 & B0);
_EQ011 = !_LC031 & _X002;
_X002 = EXP(!A2 & B1);
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( _EQ012 $ !B2);
_EQ012 = _X002 & _X003
# _LC032;
_X002 = EXP(!A2 & B1);
_X003 = EXP(!A1 & B0);
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( _EQ013 $ VCC);
_EQ013 = A2 & !B0 & !B1 & !B2
# A1 & !B0 & !B2 & _X002
# !B2 & _X002 & _X003;
_X002 = EXP(!A2 & B1);
_X003 = EXP(!A1 & B0);
-- Node name is '|LPM_ADD_SUB:335|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC002', type is buried
_LC002 = LCELL( _EQ014 $ VCC);
_EQ014 = A2 & !B0 & !B1 & !B2
# A1 & !B0 & !B2 & _X002
# !B2 & _X002 & _X003;
_X002 = EXP(!A2 & B1);
_X003 = EXP(!A1 & B0);
-- Node name is '|LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( B0 $ A2);
-- Node name is '|LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( B1 $ _EQ015);
_EQ015 = !A2 & B0;
-- Node name is '|LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( _EQ016 $ !B2);
_EQ016 = A2 & !B1
# !B0 & !B1;
-- Node name is '|LPM_ADD_SUB:445|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( _EQ017 $ VCC);
_EQ017 = A2 & !B1 & !B2
# !B0 & !B1 & !B2;
-- Node name is '~171~1'
-- Equation name is '~171~1', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ018 $ _EQ019);
_EQ018 = _X004 & _X005 & _X006 & _X007 & _X008;
_X004 = EXP( A0 & A1 & A2 & B0 & B1 & !B2 & !_LC001 & !_LC002 & _LC004 &
!_LC017 & !_LC018 & _LC024);
_X005 = EXP( A0 & !A1 & A2 & B0 & !B1 & !B2 & !_LC001 & !_LC002 & !_LC004 &
!_LC017 & !_LC018 & !_LC019 & !_LC021 & !_LC022 & !_LC023);
_X006 = EXP( A0 & !A1 & A2 & B0 & B1 & !B2 & !_LC001 & !_LC002 & _LC004 &
!_LC017 & !_LC018 & _LC024);
_X007 = EXP( A0 & !A1 & A2 & B0 & !B1 & !B2 & !_LC019 & !_LC021 & !_LC022 &
!_LC023 & !_LC024);
_X008 = EXP( A0 & A1 & A2 & B0 & B1 & B2 & !_LC024);
_EQ019 = !_LC025 & !_LC029 & _X009 & _X010 & _X011 & _X012 & _X013 &
_X014 & _X015 & _X016 & _X017;
_X009 = EXP(!A2 & B2 & !_LC024);
_X010 = EXP(!A0 & !A2 & B0 & B1 & !_LC024);
_X011 = EXP( B1 & !_LC001 & !_LC002 & !_LC004 & !_LC017 & !_LC018 & _LC024);
_X012 = EXP(!A1 & !A2 & B1 & !_LC024);
_X013 = EXP(!A1 & B1 & B2 & !_LC024);
_X014 = EXP( B0 & B1 & B2 & !_LC024);
_X015 = EXP(!A0 & !A1 & !A2 & B0 & !_LC024);
_X016 = EXP( B2 & !_LC001 & !_LC002 & !_LC017 & !_LC018 & _LC024);
_X017 = EXP(!A0 & !A1 & B0 & B2 & !_LC024);
-- Node name is '~171~2'
-- Equation name is '~171~2', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ020 $ GND);
_EQ020 = !A1 & A2 & B0 & !B1 & !B2 & !_LC001 & !_LC002 & !_LC004 &
!_LC017 & !_LC018 & !_LC019 & !_LC021 & !_LC022 & !_LC023
# !A1 & A2 & B0 & !B1 & !B2 & !_LC019 & !_LC021 & !_LC022 &
!_LC023 & !_LC024
# !A0 & A1 & B0 & !_LC001 & !_LC002 & !_LC004 & !_LC017 & !_LC018 &
_LC024
# !A0 & A2 & B0 & !_LC001 & !_LC002 & !_LC004 & !_LC017 & !_LC018 &
_LC024
# !A0 & !A1 & !A2 & B0 & !_LC001 & !_LC002 & !_LC004 & !_LC017 &
!_LC018;
-- Node name is '~171~3'
-- Equation name is '~171~3', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ021 $ GND);
_EQ021 = A2 & B0 & B1 & !_LC001 & !_LC002 & !_LC017 & !_LC018 & _LC024
# !A0 & B0 & B2 & !_LC001 & !_LC002 & !_LC004 & !_LC018 & _LC024
# !A0 & B0 & B1 & !_LC001 & !_LC002 & !_LC017 & !_LC018 & _LC024
# !A0 & B0 & B1 & B2 & !_LC001 & !_LC002 & !_LC018
# B1 & B2 & !_LC001 & !_LC002 & !_LC004 & !_LC018 & _LC024;
-- Node name is '~316~1'
-- Equation name is '~316~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ022 $ !B2);
_EQ022 = !A2 & B1 & !B2
# !A1 & B0 & !B2;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs A, B
-- _X003 occurs in LABs A, B
Project Information e:\divi\div.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,904K
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