div.vhd

通过用硬件描述语言（VHDL）描述除法器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
-----------------------------------------------------------------
entity div is
	port (
		DIVz: out STD_LOGIC;
		A: in STD_LOGIC_VECTOR (3 downto 0);
		B: in STD_LOGIC_VECTOR (3 downto 0);
		C: out STD_LOGIC_VECTOR (3 downto 0)
	);
end div;
------------------------------------------------------------------

architecture fpdiv_arch of div is
signal remainS0 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS1 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS2 : STD_LOGIC_VECTOR (5 downto 0);
signal remainS3 : STD_LOGIC_VECTOR (5 downto 0);

signal diverS0 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS1 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS2 : STD_LOGIC_VECTOR (5 downto 0);
signal diverS3 : STD_LOGIC_VECTOR (5 downto 0);

signal Q_TEMP : STD_LOGIC_VECTOR (3 downto 0);
signal Z0 : STD_LOGIC_VECTOR (2 downto 0);
signal Z1 : STD_LOGIC_VECTOR (2 downto 0);
signal ZERO : STD_LOGIC;

begin
	Z0 <=(others => '0');
	Z1 <=(others => '0');
	diverS0 <=Z0 & B(2 downto 0);
	remainS3  <=Z1& A(2 downto 0);

	diverS1 <= diverS0(4 downto 0) & '0';
	diverS2 <= diverS1(4 downto 0) & '0';
	diverS3 <= diverS2(4 downto 0) & '0';

	Q_TEMP(2) <= '1' when (remainS3 >= diverS2) else '0';
	Q_TEMP(1) <= '1' when (remainS2 >= diverS1) else '0';
	Q_TEMP(0) <= '1' when (remainS1 >= diverS0) else '0';
	
	remainS2 <= remainS3 - diverS2 when Q_TEMP(2) = '1' else remainS3;
	remainS1 <= remainS2 - diverS1 when Q_TEMP(1) = '1' else remainS2;
	remainS0 <= remainS1 - diverS0 when Q_TEMP(0) = '1' else remainS1;

	Q_TEMP(3) <= A(3) xor B(3);
	ZERO <= '1' when B(2 downto 0) = Z1 else '0';
	DIVz <= '1' when ZERO = '1' else '0';
	C <= (others => '0') when ZERO = '1' else Q_TEMP;
end fpdiv_arch;