verilog.cc

将Verilog代码转换成C++代码的软件

  {
    ostr << std::setw(indent) << "" << "<process type=\"";
    switch( type_ )
      {
      case INITIAL:
	ostr << "initial";
	break;
      case ALWAYS:
	ostr << "always";
	break;
      case TASK:
	ostr << "task\" name=\""<< name_;
	break;
      case ASSIGN:
	ostr << "assign";
	break;
      }
    ostr << "\">\n";
    stat_->toXML(ostr,indent+1);  
    ostr << std::setw(indent) << "" << "</process>\n";
  }
  void Verilog::Process::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "";
    switch( type_ )
      {
      case INITIAL:
	ostr << "initial\n";
	stat_->toVerilog(ostr,indent+1);  
	break;
      case ALWAYS:
	ostr << "always\n";
	stat_->toVerilog(ostr,indent+1);  
	break;
      case TASK:
	ostr << "task ";
	printName( ostr,name_ );
	ostr << ";\n";
	stat_->toVerilog(ostr,indent+1);
	ostr << std::setw(indent) << "endtask\n";
	break;
      case ASSIGN:
	ostr << "assign ";
	stat_->toVerilog(ostr,0);
	break;
      case PARAMETER:
	ostr << "parameter ";
	stat_->toVerilog(ostr,0);
	break;
      }
  }
  void Verilog::Process::link(Module* mod)
  {
    stat_->link(mod->net(),mod);
    stat_->chain(statChain_);
    {
      EventNetChainCB cb(eventChain_);
      stat_->callback( cb );
    }
    {
      LeftNetChainCB cb(leftChain_);
      stat_->callback( cb );
    }
    {
      RightNetChainCB cb(rightChain_);
      stat_->callback( cb );
    }
    //
    {
      NetChainCB cb(nbLeftChain_,
		    nbRightChain_,
		    bLeftChain_,
		    bRightChain_);
      stat_->callback( cb );
    }
  }
  Verilog::Process* Verilog::Process::clone(const string& hname) const
  {
    Verilog::Process* ret =new Verilog::Process();
    ret->type_ =type_;
    ret->stat_ =(stat_!=NULL) ? stat_->clone(hname) : NULL;
    ret->name_ =hname + name_;
    return ret;
  }
  bool Verilog::Process::isEdge() const
  {
    if( typeid( *stat_ )==typeid( Assign ) )
      return false;
    else if( typeid( *stat_ )==typeid( EventStatement ) )
      return ((EventStatement*)(stat_))->isEdge();
    return true;
  }
  bool Verilog::Process::isLevel() const
  {
    if( typeid( *stat_ )==typeid( Assign ) )
      return true;
    else if( typeid( *stat_ )==typeid( EventStatement ) )
      return ((EventStatement*)(stat_))->isLevel();
    return false;
  }
  bool Verilog::Process::isStorage() const
  {
    if( typeid( *stat_ )==typeid( Assign ) )
      return false;
    else if( typeid( *stat_ )==typeid( EventStatement ) )
      {
	set<const Net*>::const_iterator i;
	for( i=rightChain_.begin();i!=rightChain_.end();++i )
	  if( eventChain_.find(*i)==eventChain_.end() )
	    return true;
      }
    return false;
  }
  const Verilog::Statement* Verilog::Process::queryStatement(int type,const Net* src) const
  {
    if( (typeid(*stat_)==typeid(EventStatement)) )
      {
	EventStatement* es =(EventStatement*)stat_;
	vector<Event*>::const_iterator iii;
	for( iii=es->event().begin();iii!=es->event().end();++iii )
	  {
	    if( (*iii)->type()==type )
	      if( (typeid(*(*iii)->expression())==typeid(Identifier)) )
		if( ((Identifier*)((*iii)->expression()))->net()==src )
		  {
		    if( es->event().size()==1 )
		      {
			if( eventChain_.find((Net*)src)!=eventChain_.end() )
			  return es->statement();
		      }
		    else if( es->event().size()>1 )
		      {
			Condition* c;
			set<const Statement*>::const_iterator i;
			set<const Net*>::const_iterator ii;
			for( i=statChain_.begin();i!=statChain_.end();++i )
			  if( typeid(*(*i))==typeid(Condition) )
			    {
			      c =((Condition*)(*i));
			      set<const Net*> n;
			      c->expression()->chain(n);
			      ii =search( eventChain_.begin(),eventChain_.end(),n.begin(),n.end() );
			      if( ii!=eventChain_.end() )
				{
				  if( (*ii)==src )
				    return c->trueStatement();
				  else
				    return c->falseStatement();
				}
			      
			    }
		      }
		  }
	  }
      }
    
    return NULL;
  }
  void Verilog::Process::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////    
  // Verilog::Gate
  ////////////////////////////////////
  Verilog::Gate::~Gate()
  {
    vector<Expression*>::iterator i;
    for( i=pin_.begin();i!=pin_.end();++i )
      delete *i;
  }
  void Verilog::Gate::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////    
  // Verilog::Instance::Port
  ////////////////////////////////////
  Verilog::Instance::Port::~Port()
  {
    delete con_;
  }
  void Verilog::Instance::Port::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "" << "<port ";
    if( ref_!="" )
      ostr << "reference=\"" << ref_ << "\" ";
    if( con_!=NULL )
      {
	ostr << "connect=\"";con_->toXML(ostr); ostr << "\"";
      }
    ostr << "/>\n";
  }
  void Verilog::Instance::Port::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "";
    if( ref_!="" )
      ostr << '.' << ref_ << '(';
    if( con_!=NULL )
      con_->toVerilog(ostr);
    if( ref_!="" )
      ostr << ')';
  }
  void Verilog::Instance::Port::link(const map<string,Net*>& net,Module* mod,Module* rmod,int idx)
  {
    if( con_!=NULL )
      con_->link(net,mod);
    
    if( rmod!=NULL )
      {
	if( ref_.empty() )
	  {
	    if( idx<rmod->port().size() )
	      ref_ =rmod->port()[idx];
	  }
	
	map<string,Net*>::const_iterator i =rmod->net().find(ref_);
	if( i!=rmod->net().end() )
	  net_ =i->second;
	else
	  std::cerr << "can't link port of instance : " << ref_ << std::endl;
      }
  }
  void Verilog::Instance::Port::ungroup(Verilog::Module* mod,
					const string& cname,const string& sname)
  {
    if( ref_!="" && con_!=NULL )
      {
	string tmp =sname + ref_;
	if( net_->interface()==Verilog::Net::INPUT )
	  {
	    mod->addAssign(new Verilog::Identifier(tmp.c_str()),con_->clone(cname));
	  }
	else if( net_->interface()==Verilog::Net::OUTPUT )
	  {
	    mod->addAssign(con_->clone(cname),new Verilog::Identifier(tmp.c_str()));
	  }
	else
	  {
	    std::cerr << "can't connect type : " << "INOUT" << std::endl;
	  }
      }
  }
  Verilog::Instance::Port* Verilog::Instance::Port::clone(const string& hname) const
  {
    return new Verilog::Instance::Port(ref_.c_str(),con_->clone(hname));
  }
  void Verilog::Instance::Port::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Instance
  ////////////////////////////////////
  Verilog::Instance::~Instance()
  {
    vector<Port*>::iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      delete *i;
  }
  void Verilog::Instance::addPort(Port* p)
  {
    port_.push_back(p);
  }
  void Verilog::Instance::toXML(std::ostream& ostr,const string& name,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<instance name=\"" << name << "\" type=\"" << type_ << "\">\n";
    vector<Port*>::const_iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      (*i)->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</instance>\n";
  }
  void Verilog::Instance::toVerilog(std::ostream& ostr,const string& name,int indent) const
  {
    ostr << std::setw(indent++) << "" << type_ << ' ';
    printName( ostr,name );
    ostr << '\n';

    ostr << std::setw(indent++) << "" << "(\n";
    vector<Port*>::const_iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      {
	if( i!=port_.begin() )
	  ostr << ',' << std::endl;
	(*i)->toVerilog(ostr,indent);
      }
    ostr << std::endl;
    ostr << std::setw(--indent) << "" << ");\n";
  }
  void Verilog::Instance::link(Verilog* veri,const map<string,Net*>& net,Module* mod)
  {
    {
      map<string,Module*>::const_iterator i =veri->module().find(type_);
      if( i!=veri->module().end() )
	module_ =i->second;
      else
	std::cerr << "can't link module : " << type_ << std::endl;
    }
    {
      int idx=0;
      vector<Port*>::iterator i;
      for( i=port_.begin();i!=port_.end();++i )
	(*i)->link(net,mod,module_,idx++);
    }
  }
  Verilog::Instance* Verilog::Instance::clone(const string& hname) const
  {
    Verilog::Instance* ret =new Verilog::Instance();
    ret->type_ =type_;
    vector<Port*>::const_iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      ret->addPort( (*i)->clone(hname) );
    return ret;
  }
  void Verilog::Instance::ungroup(Verilog::Module* mod,const string& cname,const string& sname)
  {
    module_->ungroup(mod,sname);
    vector<Port*>::iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      (*i)->ungroup(mod,cname,sname);
  }
  void Verilog::Instance::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Module
  ////////////////////////////////////
  Verilog::Module::~Module()
  { 
    {
      map<string,Net*>::iterator i;
      for( i=net_.begin();i!=net_.end();++i )
	delete i->second;
    }
    {
      vector<Process*>::iterator i;
      for( i=process_.begin();i!=process_.end();++i )
	delete *i;
    }
    {
      map<string,Function*>::iterator i;
      for( i=function_.begin();i!=function_.end();++i )
	delete i->second;
    }
    {
      map<string,Instance*>::iterator i;
      for( i=instance_.begin();i!=instance_.end();++i )
	delete i->second;
    }
  }
  void Verilog::Module::addPort(const char* name)
  {
    port_.push_back(name);
  }
  void Verilog::Module::addNet(const char* name,Verilog::Net* net)
  {
    pair<map<string,Net*>::iterator,bool> ret =net_.insert( pair<string,Net*>(name,net));
  }
  Verilog::Net* Verilog::Module::newNet(const char* name,
					int type,
					Expression* msb,Expression* lsb,
					int inter,
					Expression* sa,Expression* ea,
					bool sign)
    {
      Verilog::Net* ret =NULL;
      map<string,Net*>::iterator i =net_.find(name);
      
    if( i==net_.end() )
      {
	ret =new Verilog::Net(type,msb,lsb,inter,sa,ea,sign);
	net_.insert( pair<string,Net*>(name,ret));
      }
    else
      {
	ret =i->second;
	if( ret->interface()==Net::PRIVATE )
	  ret->setInterface( inter );
	if( ret->type()==Net::IMPLICIT )
	  ret->setType( type );
	
      }
    return ret;
  }
  void Verilog::Module::addAssign(Expression* l,Expression* r)
  {
    moe::Verilog::Statement* stat =new moe::Verilog::Assign(moe::Verilog::Assign::BLOCKING,l,r);
    moe::Verilog::Process* proc =new moe::Verilog::Process(moe::Verilog::Process::ASSIGN,stat);
    
    process_.push_back(proc);
  }
  void Verilog::Module::addParameter(Expression* l,Expression* r)
  {
    moe::Verilog::Statement* stat =new moe::Verilog::Assign(moe::Verilog::Assign::BLOCKING,l,r);
    moe::Verilog::Process* proc =new moe::Verilog::Process(moe::Verilog::Process::PARAMETER,stat);
    
    process_.push_back(proc);
  }
  Verilog::Instance* Verilog::Module::newInstance(const char* name)
  {
    moe::Verilog::Instance* inst =new moe::Verilog::Instance;
    pair<map<string,Instance*>::iterator,bool> ret =instance_.insert( pair<string,Instance*>(name,inst));
    if( !ret.second )
      {
	std::cerr << "instance name repetition error : " << name << "\n";
	delete inst;
      }
    return ret.first->second;
  }
  void Verilog::Module::addProcess(Process* proc)
  {
    process_.push_back(proc);
  }
  Verilog::Function* Verilog::Module::newFunction(const char* name)
  {
    Verilog::Function* func =new Function;
    pair<map<string,Function*>::iterator,bool> ret =function_.insert( pair<string,Function*>(name,func) );
    if( !ret.second )
      {
	std::cerr << "function name repetition error : " << name << "\n";
	delete func;
      }
    return ret.first->second;
  }
  void Verilog::Module::addFunction(const char* name,Verilog::Function* func)
  {
    pair<map<string,Function*>::iterator,bool> ret =function_.insert( pair<string,Function*>(name,func) );
    if( !ret.second )
      {
	std::cerr << "function name repetition error : " << name << "\n";
	delete func;
      }
  }
  void Verilog::Module::addInstance(const char* name,moe::Verilog::Instance* inst)
  {
    pair<map<string,Instance*>::iterator,bool> ret =instance_.insert( pair<string,Instance*>(name,inst));
    if( !ret.second )
      {
	std::cerr << "instance name repetition error : " << name << "\n";
	delete inst;
      }
  }
  void Verilog::Module::toXML( std::ostream& ostr,const string& name,int indent ) const
  {
    ostr << std::setw(indent++) << "" << "<module name=\"" << name << "\">\n";
    {
      ostr << std::setw(indent++) << "" << "<port_order>\n";
      vector<string>::const_iterator i;
      for( i=port_.begin();i!=port_.end();++i )
	ostr <<  std::setw(indent) << "" << *i << std::endl;
      ostr <<  std::setw(--indent) << "" << "</port_order>\n";
    }
    {
      map<string,Net*>::const_iterator i;
      for( i=net_.begin();i!=net_.end();++i )
	i->second->toXML(ostr,i->first,indent);
    }
    {
      map<string,Function*>::const_iterator i;
      for( i=function_.begin();i!=function_.end();++i )
	i->second->toXML(ostr,indent);
    }
    {
      map<string,Instance*>::const_iterator i;
      for( i=instance_.begin();i!=instance_.end();++i )
	i->second->toXML(ostr,i->first,indent);
    }
    {
      vector<Process*>::const_iterator i;
      for( i=process_.begin();i!=process_.end();++i )
	(*i)->toXML(ostr,indent);
    }
    ostr << std::setw(--indent) << "" << "</module>\n";
  }
  void Verilog::Module::toVerilog( std::ostream& ostr,const string& name,int indent ) const
  {
    ostr << std::setw(indent++) << "" << "module ";
    printName( ostr,name );
    ostr << std::endl;

    ostr <<  std::setw(indent++) << "" << "(\n";
    vector<string>::const_iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      {
	if( i!=port_.begin() )
	  ostr << ",\n";
	ostr << std::setw(indent) << "" << *i;
      }
    ostr << std::endl;
    ostr << std::setw(--indent) << "" << ");\n";
    
    // parameter
    {
      vector<Process*>::const_iterator i;
      for( i=process_.begin();i!=process_.end();++i )
	if( (*i)->type()==Process::PARAMETER )
	  (*i)->toVerilog(ostr,indent);
    }
    // net::public
    {
      vector<string>::const_iterator i;
      map<string,Net*>::const_iterator ii;
      for( i=port_.begin();i!=port_.end();++i )
	{
	  ii =net_.find(*i);
	  if( ii!=net_.end() )
	    ii->second->toVerilog(ostr,ii->first,indent);
	}
    }
    // net::private
    {
      map<string,Net*>::const_iterator i;
      for( i=net_.begin();i!=net_.end();++i )
	{
	  if( i->second->interface()==Net::PRIVATE )
	    if( i->second->type()!=Net::PARAMETER )
	      i->second->toVerilog(ostr,i->first,indent);
	}
    }
    // function
    {
      map<string,Function*>: