verilog.cc

将Verilog代码转换成C++代码的软件

  }
  Verilog::Case::Item* Verilog::Case::Item::clone(const string& hname) const
  {
    Verilog::Case::Item* ret =new Verilog::Case::Item();
    vector<Expression*>::const_iterator i;
    for( i=expr_.begin();i!=expr_.end();++i )
      ret->expr_.push_back( (*i)->clone(hname) );
    ret->stat_ =(stat_!=NULL) ? stat_->clone(hname) : NULL;
    return ret;
  }
  void Verilog::Case::Item::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    if( stat_!=NULL )
      stat_->chain(ss);
  }
  void Verilog::Case::Item::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Case
  ////////////////////////////////////
  Verilog::Case::~Case()
  {
    delete expr_;
    vector<Item*>::iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      delete *i;
  }
  void Verilog::Case::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<case type=\"";
    switch( type_ )
      {
      case CASE:
	ostr << "case";
	break;
      case CASEX:
	ostr << "casex";
	break;
      case CASEZ:
	ostr << "casez";
	break;
      }
    ostr << "\">\n";
    
    vector<Item*>::const_iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      (*i)->toXML(ostr,indent);
    
    ostr << std::setw(--indent) << "" << "</case>\n";
  }
  void Verilog::Case::toVerilog(std::ostream& ostr,int indent) const
  {
    switch( type_ )
      {
      case CASE:
	ostr << std::setw(indent) << "" << "case(";
	break;
      case CASEX:
	ostr << std::setw(indent) << "" << "casex(";
	break;
      case CASEZ:
	ostr << std::setw(indent) << "" << "casez(";
	break;
      }
    expr_->toVerilog(ostr);
    ostr << ")\n";
    indent++;
    
    vector<Item*>::const_iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      (*i)->toVerilog(ostr,indent);
    ostr << std::setw(--indent) << "" << "endcase\n";
  }
  void Verilog::Case::link(const map<string,Net*>& net,Module* mod)
  {
    expr_->link(net,mod);
    vector<Item*>::iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      (*i)->link(net,mod);
  }
  Verilog::Statement* Verilog::Case::clone(const string& hname) const
  {
    Verilog::Case* ret =new Verilog::Case();
    ret->type_ =type_;
    ret->expr_ =(expr_!=NULL) ? expr_->clone(hname) : NULL;
    vector<Item*>::const_iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      ret->items_.push_back( (*i)->clone(hname) );
    return ret;
  }
  void Verilog::Case::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    vector<Item*>::const_iterator i;
    for( i=items_.begin();i!=items_.end();++i )
      (*i)->chain(ss);
  }
  void Verilog::Case::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Condition
  ////////////////////////////////////
  Verilog::Condition::~Condition()
  {
    delete expr_;
    delete true_;
    delete false_;
  }
  void Verilog::Condition::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<condition when=\"";
    expr_->toXML(ostr);
    ostr << "\">\n";
    ostr << std::setw(indent++) << "" << "<true>\n";
    true_->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</true>\n";
    if( false_!=NULL )
      {
	ostr << std::setw(indent++) << "" << "<false>\n";
	false_->toXML(ostr,indent);
	ostr << std::setw(--indent) << "" << "</false>\n";
      }
    ostr << std::setw(--indent) << "" << "</condition>\n";
  }
  void Verilog::Condition::toVerilog(std::ostream& ostr,int indent) const
  {
    if( indent<0 )
      indent =-indent;
    else
      ostr << std::setw(indent) << "";
    ostr << "if(";

    expr_->toVerilog(ostr);
    ostr << ")\n";
    true_->toVerilog(ostr,indent+1);
    if( false_!=NULL )
      {
	ostr << std::setw(indent) << "" << "else";
	if( typeid(*false_)==typeid(Verilog::Condition) )
	  {
	    ostr << ' ';
	    false_->toVerilog(ostr,-indent);
	  }
	else
	  {
	    ostr << '\n';
	    false_->toVerilog(ostr,indent+1);
	  }
      }
  }
  void Verilog::Condition::link(const map<string,Net*>& net,Module* mod)
  {
    expr_->link(net,mod);
    true_->link(net,mod);
    if( false_!=NULL )
      false_->link(net,mod);
  }
  Verilog::Statement* Verilog::Condition::clone(const string& hname) const
  {
    Verilog::Condition* ret =new Verilog::Condition();
    ret->expr_ =(expr_!=NULL) ? expr_->clone(hname) : NULL;
    ret->true_ =(true_!=NULL) ? true_->clone(hname) : NULL;
    ret->false_ =(false_!=NULL) ? false_->clone(hname) : NULL;
    return ret;
  }
  void Verilog::Condition::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    true_->chain(ss);
    if( false_!=NULL )
      false_->chain(ss);
  }
  void Verilog::Condition::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::EventStatement
  ////////////////////////////////////
  Verilog::EventStatement::~EventStatement()
  {
    delete stat_;
    vector<Event*>::iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      delete *i;
  }
  void Verilog::EventStatement::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<event when=\"";
    vector<Event*>::const_iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      {
	if( i!=event_.begin() )
	  ostr << " or ";
	(*i)->toXML(ostr);
      }
    ostr << "\">\n";
    if( stat_!=NULL )
      stat_->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</event>\n";
  }
  void Verilog::EventStatement::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "" << "@(";
    vector<Event*>::const_iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      {
	if( i!=event_.begin() )
	  ostr << " or ";
	(*i)->toVerilog(ostr);
      }
    ostr << ")\n";
    if( stat_!=NULL )
      stat_->toVerilog(ostr,indent+1);
  }
  void Verilog::EventStatement::link(const map<string,Net*>& net,Module* mod)
  {
    vector<Event*>::iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      (*i)->link(net,mod);
    stat_->link(net,mod);

    { // Verilog-2000 enhancements
      if( event_.empty() )
	{
	  set<const Net*> chain;
	  RightNetChainCB rnccb( chain );
	  stat_->callback( rnccb );

	  set<const Net*> lchain;
	  LeftNetChainCB lnccb( lchain );
	  stat_->callback( lnccb );

	  set<const Net*>::const_iterator i;
	  for( i=chain.begin();i!=chain.end();++i )
	    {
	      if( lchain.find(*i)==lchain.end() )
		{
		  event_.push_back( new Event(Event::ANYEDGE,
					      new Identifier(mod->findName(*i))) );
		  event_.back()->link(net,mod);	
		}      
	    }
	}
    }
  }
  Verilog::Statement* Verilog::EventStatement::clone(const string& hname) const
  {
    Verilog::EventStatement* ret =new Verilog::EventStatement();
    vector<Event*>::const_iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      ret->event_.push_back( (Event*)(*i)->clone(hname) );
    ret->stat_ =stat_->clone(hname);
    return ret;
  }
  void Verilog::EventStatement::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    if( stat_!=NULL )
      stat_->chain(ss);
  }
  bool Verilog::EventStatement::isEdge() const
  {
    vector<Event*>::const_iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      if( ( (*i)->type()!=Event::POSEDGE )&&
	  ( (*i)->type()!=Event::NEGEDGE ) )
	return false;
    return true;
  }
  bool Verilog::EventStatement::isLevel() const
  {
    vector<Event*>::const_iterator i;
    for( i=event_.begin();i!=event_.end();++i )
      if( (*i)->type()!=Event::ANYEDGE )
	return false;
    return true;
  }
  void Verilog::EventStatement::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Assign
  ////////////////////////////////////
  Verilog::Assign::~Assign()
  {
    delete lval_;
    delete rval_;
  }
  void Verilog::Assign::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<assign type=\"";
    switch( type_ )
      {
      case BLOCKING:    ostr << "blocking\">\n"; break;
      case NONBLOCKING: ostr << "nonblocking\">\n"; break;
      }
    set<const Net*> lc;
    lval_->chain(lc);
    ostr << std::setw(indent+1) << "" << "<left chain=\"" << lc.size() << "\">";
    lval_->toXML(ostr);
    ostr << "</left>\n";
    set<const Net*> rc;
    rval_->chain(rc);
    ostr << std::setw(indent+1) << "" << "<right chain=\"" << rc.size() << "\">";
    rval_->toXML(ostr);
    ostr << "</right>\n";
    ostr << std::setw(--indent) << "" << "</assign>\n";
  }
  void Verilog::Assign::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "";
    lval_->toVerilog(ostr);
    switch( type_ )
      {
      case BLOCKING: ostr << " ="; break;
      case NONBLOCKING: ostr << " <=";
	if( source_->dec_tpd_ )
	  ostr << "`TPD ";
	break;
      }
    rval_->toVerilog(ostr);
    ostr << ";\n";
  }
  void Verilog::Assign::link(const map<string,Net*>& net,Module* mod)
  {
    lval_->link(net,mod);
    rval_->link(net,mod);
  }
  Verilog::Statement* Verilog::Assign::clone(const string& hname) const
  {
    return new Verilog::Assign( type_,
				(lval_!=NULL) ? lval_->clone(hname) : NULL,
				(rval_!=NULL) ? rval_->clone(hname) : NULL );
  }
  bool Verilog::Assign::isSimpleLeft() const
  {
    if( (typeid(*lval_)==typeid(Verilog::Identifier)) )
      {
	Verilog::Identifier* l=(Verilog::Identifier*)lval_;
	if( (l->msb()==NULL)&&
	    (l->lsb()==NULL)&&
	    (l->idx()==NULL) )
	  return true;
      }
    return false;
  }
  bool Verilog::Assign::isSimpleRight() const
  {
    if( (typeid(*rval_)==typeid(Verilog::Identifier)) )
      {
	Verilog::Identifier* r=(Verilog::Identifier*)rval_;
	
	if( (r->msb()==NULL)&&
	    (r->lsb()==NULL)&&
	    (r->idx()==NULL) )
	  return true;
      }
    return false;
  }
  bool Verilog::Assign::isSimple() const
  {
    return (isSimpleLeft()&&isSimpleRight());
  }
  void Verilog::Assign::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
  }
  void Verilog::Assign::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::For
  ////////////////////////////////////
  Verilog::For::For(Identifier* i1,Expression* e1,
		    Expression* e2,
		    Identifier* i2,Expression* e3,
		    Statement* s)
  {
      {
	ita_ =i1;
	begin_ =e1;
	cond_ =e2;
	reach_ =e3;
	stat_ =s;
      }
      //std::cerr << "can't support a complexed expression in for-loop\n";
  }
  Verilog::For::~For()
  {
    delete ita_;
    delete begin_;
    delete cond_;
    delete reach_;
    delete stat_;
  }
  void Verilog::For::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<for ";
    ostr << "iterator=\"";ita_->toXML(ostr);ostr << "\" ";
    ostr << "begin=\"";begin_->toXML(ostr);ostr << "\" ";
    ostr << "condition=\"";  cond_->toXML(ostr);ostr << "\" ";
    ostr << "reach=\"";reach_->toXML(ostr);ostr << "\" ";
    ostr << ">\n";
    stat_->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</for>\n";
  }
  void Verilog::For::toVerilog(std::ostream& ostr,int indent) const
  {
    if( indent<0 )
      indent =-indent;
    else
      ostr << std::setw(indent) << "";

    ostr << "for(";
    ita_->toVerilog(ostr);ostr << "=";begin_->toVerilog(ostr);ostr << ";";
    cond_->toVerilog(ostr);ostr << ";";
    ita_->toVerilog(ostr);ostr << "=";reach_->toVerilog(ostr);
    ostr << ")\n";
    stat_->toVerilog(ostr,indent+1);
  }
  void Verilog::For::link(const map<string,Net*>& net,Module* mod)
  {
    ita_->link(net,mod);
    begin_->link(net,mod);
    cond_->link(net,mod);
    reach_->link(net,mod);
    stat_->link(net,mod);
  }
  Verilog::Statement* Verilog::For::clone(const string& hname) const
  {
    Verilog::For* ret =new Verilog::For();
    ret->ita_   =(Verilog::Identifier*)ita_->clone(hname);
    ret->begin_ =begin_->clone(hname);
    ret->cond_  =cond_->clone(hname);
    ret->reach_ =reach_->clone(hname);
    ret->stat_  =stat_->clone(hname);
    return ret;
  }
  void Verilog::For::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    //
    stat_->chain(ss);
    //
  }
  void Verilog::For::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Function
  ////////////////////////////////////
  Verilog::Function::~Function()
  {
    map<string,Net*>::iterator i;
    for( i=net_.begin();i!=net_.end();++i )
      delete i->second;
    delete stat_;
  }
  void Verilog::Function::addNet(const char* name,Verilog::Net* net)
  {
    port_.push_back(name);
    pair<map<string,Net*>::iterator,bool> ret =net_.insert( pair<string,Net*>(name,net) );
    if( !ret.second )
      {
	if( ret.first->second->interface()==Net::PRIVATE )
	  ret.first->second->setInterface( net->interface() );
	if( ret.first->second->type()==Net::IMPLICIT )
	  ret.first->second->setType( net->type() );
      }
  }
  void Verilog::Function::toXML(std::ostream& ostr,int indent) const
  {
  }
  void Verilog::Function::toVerilog(std::ostream& ostr,int indent) const
  {
    vector<string>::const_iterator i;
    for( i=port_.begin();i!=port_.end();++i )
      {
	net_.find(*i)->second->toVerilog(ostr,*i,indent);
	if( i==port_.begin() )
	  indent++;
      }

    stat_->toVerilog(ostr,indent--);
    ostr << std::setw(indent) << "" << "endfunction\n";
  }
  void Verilog::Function::link(Module* mod)
  {
    stat_->link(net_,mod);
  }
  Verilog::Function* Verilog::Function::clone(const string& hname) const
  {
    string tmp;
    Verilog::Function* ret =new Verilog::Function();
    map<string,Net*>::const_iterator i;
    for( i=net_.begin();i!=net_.end();++i )
      {
	tmp =hname + i->first;
	ret->port_.push_back(tmp);
	ret->net_[tmp] =i->second->clone(hname);
      }
    ret->stat_ =(stat_!=NULL) ? stat_->clone(hname) : NULL;
    return ret;
  }
  void Verilog::Function::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  //Verilog::Process
  ////////////////////////////////////
  Verilog::Process::~Process()
  {
    delete stat_;
  }
  void Verilog::Process::toXML(std::ostream& ostr,int indent) const