verilog.cc

将Verilog代码转换成C++代码的软件

  void Verilog::Ternary::toXML(std::ostream& ostr) const
  {
    expr_->toXML(ostr);
    ostr << " ? (";
    true_->toXML(ostr);
    ostr << ") : (";
    false_->toXML(ostr);
    ostr << ')';
  }
  void Verilog::Ternary::toVerilog(std::ostream& ostr) const
  {
    ostr << '(';
    expr_->toVerilog(ostr);
    ostr << " ? ";
    true_->toVerilog(ostr);
    ostr << " : ";
    false_->toVerilog(ostr);
    ostr << ')';
  }
  void Verilog::Ternary::link(const map<string,Net*>& net,Module* mod)
  {
    expr_->link(net,mod);
    true_->link(net,mod);
    if( false_!=NULL )
      false_->link(net,mod);
  }
  Verilog::Expression* Verilog::Ternary::clone(const string& hname) const
  {
    return new Verilog::Ternary( expr_->clone(hname),
				 (true_!=NULL) ? true_->clone(hname) : NULL,
				 (false_!=NULL) ? false_->clone(hname) : NULL );
  }
  Verilog::Expression* Verilog::Ternary::clone() const
  {
    return new Verilog::Ternary( expr_->clone(),
				 (true_!=NULL) ? true_->clone() : NULL,
				 (false_!=NULL) ? false_->clone() : NULL );
  }
  void Verilog::Ternary::chain(set<const Net*>& ev) const
  {
    if( expr_!=NULL )
      expr_->chain(ev);
    if( true_!=NULL )
      true_->chain(ev);
    if( false_!=NULL )
      false_->chain(ev);
  }
  void Verilog::Ternary::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    if( expr_!=NULL )
      expr_->chain(ev);
    if( true_!=NULL )
      true_->chain(ev);
    if( false_!=NULL )
      false_->chain(ev);
  }
  void Verilog::Ternary::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::CallFunction
  ////////////////////////////////////
  Verilog::CallFunction::~CallFunction()
  {
    vector<Expression*>::iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      delete (*i);
  }
  void Verilog::CallFunction::toXML(std::ostream& ostr) const
  {
    ostr << name_ << '(';
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      {
	if( i!=parms_.begin() )
	  ostr << ',';
	(*i)->toXML(ostr);
      }
    ostr << ')';
  }
  void Verilog::CallFunction::toVerilog(std::ostream& ostr) const
  {
    printName( ostr,name_ );

    ostr << '(';
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      {
	if( i!=parms_.begin() )
	  ostr << ',';
	(*i)->toVerilog(ostr);
      }
    ostr << ')';
  }
  void Verilog::CallFunction::link(const map<string,Net*>& net,Module* mod)
  {
    {
      vector<Expression*>::iterator i;
      for( i=parms_.begin();i!=parms_.end();++i )
	(*i)->link(net,mod);
    }
    {
      map<string,Function*>::const_iterator i =mod->function().find(name_);
      if( i!=mod->function().end() )
	{
	  func_ =i->second;
	  map<string,Net*>::const_iterator ii =func_->net().find(name_);
	  if( ii!=func_->net().end() )
	    net_ =ii->second;
	  else
	    std::cerr << "can't link port of function : " << name_ << std::endl;
	}
      else
	std::cerr << "can't link function : " << name_ << std::endl;
    }
  }
  Verilog::Expression* Verilog::CallFunction::clone(const string& hname) const
  {
    Verilog::CallFunction* ret =new Verilog::CallFunction();
    ret->name_ =hname + name_;
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      ret->parms_.push_back( (*i)->clone(hname) );
    return ret;
  }
  Verilog::Expression* Verilog::CallFunction::clone() const
  {
    Verilog::CallFunction* ret =new Verilog::CallFunction();
    ret->name_ =name_;
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      ret->parms_.push_back( (*i)->clone() );
    return ret;
  }
  void Verilog::CallFunction::chain(set<const Net*>& ev) const
  {
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      (*i)->chain(ev);
  }
  void Verilog::CallFunction::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    vector<Expression*>::const_iterator i;
    for( i=parms_.begin();i!=parms_.end();++i )
      (*i)->chain(ev);
  }
  void Verilog::CallFunction::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Net
  ////////////////////////////////////
  void Verilog::Net::toXML(std::ostream& ostr,const string& name,int indent) const
  {
    ostr << std::setw(indent) << "" << "<net name=\"" << name << "\" ";
    
    if( (msb_!=NULL)&&(lsb_!=NULL) )
      {
	ostr << "bitrange=\"";
	msb_->toXML(ostr);
	ostr << ' ';
	lsb_->toXML(ostr);
	ostr << "\" ";
      }
    
    if( (sa_!=NULL)&&(ea_!=NULL) )
      {
	ostr << "addressrange=\"";
	sa_->toXML(ostr);
	ostr << ' ';
	ea_->toXML(ostr);
	ostr << "\" ";
      }

    ostr << "type=\"";
    switch( type_ )
      {
      case IMPLICIT:
	ostr << "implicit";break;
      case WIRE:
	ostr << "wire";break;
      case TRI:
	ostr << "tri";break;
      case TRI1:
	ostr << "tri1";break;
      case SUPPLY0:
	ostr << "supply0";break;
      case WAND:
	ostr << "wand";break;
      case TRIAND:
	ostr << "triand";break;
      case TRI0:
	ostr << "tri0";break;
      case SUPPLY1:
	ostr << "supply1";break;
      case WOR: 
	ostr << "wor";break;
      case TRIOR:
	ostr << "trior";break;
      case REG:
	ostr << "reg";break;
      case INTEGER:
	ostr << "integer";break;
      case REAL:
	ostr << "real";break;
	//      case PARAMETER:
	//	ostr << "parameter";break;
      }
    ostr << "\" ";
    
    ostr << "interface=\"";
    switch( interface_ )
      {
      case PRIVATE:
	ostr << "private";break;
      case INPUT:
	ostr << "input";break;
      case OUTPUT:
	ostr << "output";break;
      case INOUT:
	ostr << "inout";break;
      }
    ostr << "\" ";
    
    ostr << "/>\n";
  }
  void Verilog::Net::toVerilog(std::ostream& ostr,const string& name,int indent) const
  {
    if( interface_!=PRIVATE )
      {
	ostr << std::setw(indent) << "";
	switch( interface_ )
	  {
	  case INPUT:
	    ostr << "input";break;
	  case OUTPUT:
	    {
	      if( type_==FUNCTION )
		ostr << "function";
	      else
		ostr << "output";
	    }
	    break;
	  case INOUT:
	    ostr << "inout";break;
	  }
	
	if( (msb_!=NULL)&&(lsb_!=NULL) )
	  {
	    ostr << ' ' << '[';
	    msb_->toVerilog(ostr);
	    ostr << ':';
	    lsb_->toVerilog(ostr);
	    ostr << ']';
	  }
	ostr << ' ';
	printName( ostr,name );
	ostr << ";\n";
      }
    
    switch( type_ )
      {
      case HIDDEN:
	break;

      case IMPLICIT:
	if( interface_!=PRIVATE )
	  break;
      case WIRE:
      case PARAMETER:
      case TRI:
      case TRI1:
      case SUPPLY0:
      case WAND:
      case TRIAND:
      case TRI0:
      case SUPPLY1:
      case WOR: 
      case TRIOR:
      case REG:
      case INTEGER:
	ostr << std::setw(indent) << "";
	switch( type_ )
	  {
	  case IMPLICIT:
	    ostr << "wire";break;
	  case WIRE:
	    ostr << "wire";break;
	  case PARAMETER:
	    ostr << "parameter";break;
	  case TRI:
	    ostr << "tri";break;
	  case TRI1:
	    ostr << "tri1";break;
	  case SUPPLY0:
	    ostr << "supply0";break;
	  case WAND:
	    ostr << "wand";break;
	  case TRIAND:
	    ostr << "triand";break;
	  case TRI0:
	    ostr << "tri0";break;
	  case SUPPLY1:
	    ostr << "supply1";break;
	  case WOR: 
	    ostr << "wor";break;
	  case TRIOR:
	    ostr << "trior";break;
	  case REG:
	    ostr << "reg";break;
	  case INTEGER:
	    ostr << "integer";break;
	  }

	if( sign_ )
	  ostr << " signed";
	
	if( (msb_!=NULL)&&(lsb_!=NULL) )
	  {
	    ostr << ' ' << '[';
	    msb_->toVerilog(ostr);
	    ostr << ':';
	    lsb_->toVerilog(ostr);
	    ostr << ']';
	  }

	ostr << ' ';
	printName( ostr,name );
	
	if( (sa_!=NULL)&&(ea_!=NULL) )
	  {
	    ostr << '[';
	    sa_->toVerilog(ostr);
	    ostr << ':';
	    ea_->toVerilog(ostr);
	    ostr << ']';
	  }
	ostr << ";\n";
	break;
      }
  }
  void Verilog::Net::link(const map<string,Net*>& net,Module* mod)
    {
      if( msb_!=NULL )
	msb_->link(net,mod);
      if( lsb_!=NULL )
	lsb_->link(net,mod);

      if( sa_!=NULL )
	sa_->link(net,mod);
      if( ea_!=NULL )
	ea_->link(net,mod);
    }
  Verilog::Net* Verilog::Net::clone(const string& hname) const
    {
      Verilog::Net* ret =new Net
	(
	 type_,
	 ((msb_!=NULL) ? msb_->clone(hname) : NULL),
	 ((lsb_!=NULL) ? lsb_->clone(hname) : NULL),
	 interface_,
	 ((sa_!=NULL) ? sa_->clone(hname) : NULL),
	 ((ea_!=NULL) ? ea_->clone(hname) : NULL),
	 sign_
	 );
      return ret;
    }
  Verilog::Net* Verilog::Net::clone() const
    {
      Verilog::Net* ret =new Net
	(
	 type_,
	 ((msb_!=NULL) ? msb_->clone() : NULL),
	 ((lsb_!=NULL) ? lsb_->clone() : NULL),
	 interface_,
	 ((sa_!=NULL) ? sa_->clone() : NULL),
	 ((ea_!=NULL) ? ea_->clone() : NULL),
	 sign_
	 );
      return ret;
    }
  void Verilog::Net::callback(Callback& cb) const
    {
      cb.trap( this );
    }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Block
  ////////////////////////////////////
  Verilog::Block::~Block()
  {
    vector<Statement*>::iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      delete *i;
  }
  void Verilog::Block::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<block>\n";
    vector<Statement*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</block>\n";
  }
  void Verilog::Block::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "begin";
    if( name_.empty() )
      ostr << '\n';
    else
      ostr << " : " << name_ << '\n';

    // net::temporal
    {
      map<string,Net*>::const_iterator i;
      for( i=net_.begin();i!=net_.end();++i )
	{
	  i->second->toVerilog(ostr,i->first,indent);
	}
    }

    vector<Statement*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->toVerilog(ostr,indent);
    ostr << std::setw(--indent) << "" << "end\n";
  }
  void Verilog::Block::link(const map<string,Net*>& net,Module* mod)
  {
    vector<Statement*>::iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->link(net,mod);
  }
  Verilog::Statement* Verilog::Block::clone(const string& hname) const
  {
    Verilog::Block* ret =new Verilog::Block(type_);
    ret->name_ =hname + name_;
    {
      vector<Statement*>::const_iterator i;
      for( i=list_.begin();i!=list_.end();++i )
	ret->list_.push_back( (*i)->clone(hname) );
    }
    {
      map<string,Net*>::const_iterator i;
      for( i=net_.begin();i!=net_.end();++i )
	ret->net_.insert( pair<string,Net*>(i->first,i->second->clone(hname)) );
    }
    return ret;
  }
  void Verilog::Block::chain(set<const Statement*>& ss) const
  {
    ss.insert((Statement*)this);
    vector<Statement*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->chain(ss);
  }
  void Verilog::Block::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Case::Item
  ////////////////////////////////////
  Verilog::Case::Item::~Item()
  {
    vector<Expression*>::iterator i;
    for( i=expr_.begin();i!=expr_.end();++i )
      delete *i;
  }
  void Verilog::Case::Item::toXML(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent++) << "" << "<item ";
    ostr << "condition=\"";
    vector<Expression*>::const_iterator i;
    for( i=expr_.begin();i!=expr_.end();++i )
      {
	if( i!=expr_.begin() )
	  ostr << ',';
	(*i)->toXML(ostr);
      }
    ostr << "\"";
    ostr << ">\n";
    stat_->toXML(ostr,indent);
    ostr << std::setw(--indent) << "" << "</item>\n";
  }
  void Verilog::Case::Item::toVerilog(std::ostream& ostr,int indent) const
  {
    ostr << std::setw(indent) << "";
    if( expr_.empty() )
      {
	ostr << "default";
      }
    else
      {
	vector<Expression*>::const_iterator i;
	for( i=expr_.begin();i!=expr_.end();++i )
	  {
	    if( i!=expr_.begin() )
	      {
		ostr << ",\n";
		ostr << std::setw(indent) << "";
	      }
	    (*i)->toVerilog(ostr);
	  }
      }
    ostr << " :";


    if( typeid(*stat_)==typeid(Verilog::Assign) )
      indent =1;
    else
      {
	ostr << '\n';
	indent++;
      }

    stat_->toVerilog(ostr,indent);
  }
  void Verilog::Case::Item::link(const map<string,Net*>& net,Module* mod)
  {
    vector<Expression*>::iterator i;
    for( i=expr_.begin();i!=expr_.end();++i )
      (*i)->link(net,mod);
    stat_->link(net,mod);