verilog.cc

将Verilog代码转换成C++代码的软件

  ////////////////////////////////////
  Verilog::Concat::~Concat()
  {
    vector<Expression*>::iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      delete *i;
  }
  void Verilog::Concat::toXML(std::ostream& ostr) const
  {
    if( repeat_!=NULL )
      {
	ostr << '{';
	repeat_->toXML(ostr);
      }
    
    ostr << '{';
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      {
	if( i!=list_.begin() )
	  ostr << ',';
	(*i)->toXML(ostr);
      }
    
    ostr << '}';
    if( repeat_!=NULL )
      ostr << '}';
  }
  void Verilog::Concat::toVerilog(std::ostream& ostr) const
  {
    if( repeat_!=NULL )
      {
	ostr << '{';
	repeat_->toVerilog(ostr);
      }
    
    ostr << '{';
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      {
	if( i!=list_.begin() )
	  ostr << ',';
	(*i)->toVerilog(ostr);
      }
    
    ostr << '}';
    if( repeat_!=NULL )
      ostr << '}';
  }
  void Verilog::Concat::link(const map<string,Net*>& net,Module* mod)
  {
    if( repeat_!=NULL )
      repeat_->link(net,mod);
    vector<Expression*>::iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->link(net,mod);
  }
  unsigned int Verilog::Concat::width() const
  {
    unsigned int ret=0;
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      ret +=(*i)->width();
    
    if( repeat_!=NULL )
      ret *=repeat_->calcConstant();
    
    return ret;
  }
  Verilog::Expression* Verilog::Concat::clone(const string& hname) const
  {
    Verilog::Concat* ret =new Verilog::Concat;
    if( repeat_!=NULL )
      ret->repeat_ =repeat_->clone(hname);
    
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      ret->list_.push_back( (*i)->clone(hname) );
    
    return ret;
  }
  Verilog::Expression* Verilog::Concat::clone() const
  {
    Verilog::Concat* ret =new Verilog::Concat;
    if( repeat_!=NULL )
      ret->repeat_ =repeat_->clone();
    
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      ret->list_.push_back( (*i)->clone() );
    
    return ret;
  }
  void Verilog::Concat::chain(set<const Net*>& ev) const
  {
    if( repeat_!=NULL )
      repeat_->chain(ev);
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->chain(ev);
  }
  void Verilog::Concat::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    if( repeat_!=NULL )
      repeat_->chain(ev);
    vector<Expression*>::const_iterator i;
    for( i=list_.begin();i!=list_.end();++i )
      (*i)->chain(ev);
  }
  void Verilog::Concat::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Event
  ////////////////////////////////////
  Verilog::Event::~Event()
  {
    delete expr_;
  }
  void Verilog::Event::toXML(std::ostream& ostr) const
  {
    switch( type_ )
      {
      case POSEDGE:
	ostr << "posedge ";
	break;
      case NEGEDGE:
	ostr << "negedge ";
	break;
      }
    expr_->toXML(ostr);
  }
  void Verilog::Event::toVerilog(std::ostream& ostr) const
  {
    switch( type_ )
      {
      case POSEDGE:
	ostr << "posedge ";
	break;
      case NEGEDGE:
	ostr << "negedge ";
	break;
      }
    expr_->toVerilog(ostr);
  }
  void Verilog::Event::link(const map<string,Net*>& net,Module* mod)
  {
    expr_->link(net,mod);
  }
  Verilog::Expression* Verilog::Event::clone(const string& hname) const
  {
    return new Verilog::Event(type_,
			      (expr_!=NULL) ? expr_->clone(hname) : NULL );
  }
  Verilog::Expression* Verilog::Event::clone() const
  {
    return new Verilog::Event(type_,
			      (expr_!=NULL) ? expr_->clone() : NULL );
  }
  void Verilog::Event::chain(set<const Net*>& ev) const
  {
    if( expr_!=NULL )
      expr_->chain(ev);
  }
  void Verilog::Event::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    if( expr_!=NULL )
      expr_->chain(ev);
  }
  void Verilog::Event::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Unary
  ////////////////////////////////////
  Verilog::Unary::~Unary()
  {
    delete expr_;
  }
  unsigned int Verilog::Unary::width() const
  {
    unsigned int w =expr_->width();

    switch( op_ )
      {
      case Expression::ArithmeticMinus:
	w =expr_->width();
	break;
      case Expression::BitwiseNegation:
	w =expr_->width();
	break;
      case Expression::LogicalNegation:
      case Expression::ReductionAND:
      case Expression::ReductionOR:
      case Expression::ReductionXOR:
      case Expression::ReductionNAND:
      case Expression::ReductionNOR:
      case Expression::ReductionNXOR:
	w =1;
	break;

      case Expression::CastSigned:
      case Expression::CastUnsigned:
	w =expr_->width();
	break;
	
      default:
	w =1;
	break;
      }

    return w;
  }
  uint64_t Verilog::Unary::calcConstant() const
  {
    int ret;
    switch( op_ )
      {
      case ArithmeticMinus:
	ret =-expr_->calcConstant();
	break;
      default:
	ret =expr_->calcConstant();
	break;
      }
    return ret;
  }
  void Verilog::Unary::toXML(std::ostream& ostr) const
  {
    ostr << opToken_[op_];
    ostr << '(';
    expr_->toXML(ostr);
    ostr << ')';
  }
  void Verilog::Unary::toVerilog(std::ostream& ostr) const
  {
    switch( op_ )
      {
      case Expression::CastSigned:
      case Expression::CastUnsigned:
	ostr << opToken_[op_];
	ostr << '(';
	break;
	
      default:
	ostr << '(';
	ostr << opToken_[op_];
	break;
      }
    
    expr_->toVerilog(ostr);
    ostr << ')';
  }
  const char* Verilog::Unary::opToken() const
  {
    return opToken_[op_];
  }
  const char* Verilog::Unary::opName() const
  {
    return opName_[op_];
  }
  void Verilog::Unary::link(const map<string,Net*>& net,Module* mod)
  {
    expr_->link(net,mod);
  }
  Verilog::Expression* Verilog::Unary::clone(const string& hname) const
  {
    return new Verilog::Unary(op_,
			      (expr_!=NULL) ? expr_->clone(hname) : NULL );
  }
  Verilog::Expression* Verilog::Unary::clone() const
  {
    return new Verilog::Unary(op_,
			      (expr_!=NULL) ? expr_->clone() : NULL );
  }
  void Verilog::Unary::chain(set<const Net*>& ev) const
  {
    if( expr_!=NULL )
      expr_->chain(ev);
  }
  void Verilog::Unary::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    if( expr_!=NULL )
      expr_->chain(ev);
  }
  void Verilog::Unary::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Binary
  ////////////////////////////////////
  Verilog::Binary::~Binary()
  {
    delete left_;
    delete right_;
  }
  unsigned int Verilog::Binary::width() const
  {
    unsigned int w;

    switch( op_ )
      {
      case ArithmeticMultiply:
	w =left_->width()+right_->width();
	break;
      case ArithmeticDivide:
	w =max( left_->width(),right_->width() );
	break;
      case ArithmeticModulus:
	w =max( left_->width(),right_->width() );
	break;
      case ArithmeticAdd:
	w =max( left_->width(),right_->width() )+1;
	break;
      case ArithmeticMinus:
	//	w =max( left_->width(),right_->width() ); ?? 
	w =max( left_->width(),right_->width() )+1;
	break;

      case ArithmeticLeftShift:
	w =max( left_->width(),right_->width() );
	break;
      case ArithmeticRightShift:
	w =max( left_->width(),right_->width() );
	break;
      case ArithmeticPower:
	w =left_->width()*right_->width();
	break;

      case BitwiseAND:
      case BitwiseOR:
      case BitwiseNOR:
      case BitwiseNXOR:
      case BitwiseXOR:
	w =max( left_->width(),right_->width() );
	break;

      case LeftShift:
      case RightShift:
	w =left_->width();
	break;

      case LogicalEquality:
      case CaseEquality:
      case LessEqual:
      case GreaterEqual:
      case LogicalInequality:
      case CaseInequality:
      case LogicalOR:
      case LogicalAND:
      case LessThan:
      case GreaterThan:
	w =1;
	break;

      default:
	w =0;
	break;
      }

    return w;
  }
  uint64_t Verilog::Binary::calcConstant() const
  {
    int ret;
    switch( op_ )
      {
      case BitwiseXOR:
	ret =left_->calcConstant() ^ right_->calcConstant();
	break;
      case ArithmeticMultiply:
	ret =left_->calcConstant() * right_->calcConstant();
	break;
      case ArithmeticDivide:
	ret =left_->calcConstant() / right_->calcConstant();
	break;
      case ArithmeticModulus:
	ret =left_->calcConstant() % right_->calcConstant();
	break;
      case ArithmeticAdd:
	ret =left_->calcConstant() + right_->calcConstant();
	break;
      case ArithmeticMinus:
	ret =left_->calcConstant() - right_->calcConstant();
	break;

      case ArithmeticLeftShift:
	ret =left_->calcConstant() << right_->calcConstant();
	break;
      case ArithmeticRightShift:
	ret =left_->calcConstant() >> right_->calcConstant();
	break;
      case ArithmeticPower:
	ret =(int)pow((double)left_->calcConstant(),(double)right_->calcConstant());
	break;

      case BitwiseAND:
	ret =left_->calcConstant() & right_->calcConstant();
	break;
      case BitwiseOR:
	ret =left_->calcConstant() | right_->calcConstant();
	break;
      case BitwiseNOR:
	ret =~(left_->calcConstant() | right_->calcConstant());
	break;
      case BitwiseNXOR:
	ret =~(left_->calcConstant() ^ right_->calcConstant());
	break;
      case LessThan:
	ret =left_->calcConstant() < right_->calcConstant();
	break;
      case GreaterThan:
	ret =left_->calcConstant() > right_->calcConstant();
	break;
      case LeftShift:
	ret =left_->calcConstant() << right_->calcConstant();
	break;
      case RightShift:
	ret =left_->calcConstant() >> right_->calcConstant();
	break;
      case LogicalEquality:
	ret =left_->calcConstant() == right_->calcConstant();
	break;
      case CaseEquality:
	ret =left_->calcConstant() == right_->calcConstant();
	break;
      case LessEqual:
	ret =left_->calcConstant() <= right_->calcConstant();
	break;
      case GreaterEqual:
	ret =left_->calcConstant() >= right_->calcConstant();
	break;
      case LogicalInequality:
	ret =left_->calcConstant() != right_->calcConstant();
	break;
      case CaseInequality:
	ret =left_->calcConstant() != right_->calcConstant();
	break;
      case LogicalOR:
	ret =left_->calcConstant() || right_->calcConstant();
	break;
      case LogicalAND:
	ret =left_->calcConstant() && right_->calcConstant();
	break;
      default:
	ret =0;
	break;
      }
    return ret;
  }
  void Verilog::Binary::toXML(std::ostream& ostr) const
  {
    ostr << '(';
    left_->toXML(ostr);
    ostr << opToken_[op_];
    right_->toXML(ostr);
    ostr << ')';
  }
  void Verilog::Binary::toVerilog(std::ostream& ostr) const
  {
    ostr << '(';
    left_->toVerilog(ostr);
    ostr << opToken_[op_];
    right_->toVerilog(ostr);
    ostr << ')';
  }
  const char* Verilog::Binary::opToken() const
  {
    return opToken_[op_];
  }
  const char* Verilog::Binary::opName() const
  {
    return opName_[op_];
  }
  void Verilog::Binary::link(const map<string,Net*>& net,Module* mod)
  {
    left_->link(net,mod);
    right_->link(net,mod);
  }
  Verilog::Expression* Verilog::Binary::clone(const string& hname) const
  {
    return new Verilog::Binary( op_,
				(left_!=NULL) ? left_->clone(hname) : NULL,
				(right_!=NULL) ? right_->clone(hname) : NULL );
  }
  Verilog::Expression* Verilog::Binary::clone() const
  {
    return new Verilog::Binary( op_,
				(left_!=NULL) ? left_->clone() : NULL,
				(right_!=NULL) ? right_->clone() : NULL );
  }
  void Verilog::Binary::chain(set<const Net*>& ev) const
  {
    if( left_!=NULL )
      left_->chain(ev);
    if( right_!=NULL )
      right_->chain(ev);
  }
  void Verilog::Binary::chain(set<const Expression*>& ev) const
  {
    ev.insert((Expression*)this);
    if( left_!=NULL )
      left_->chain(ev);
    if( right_!=NULL )
      right_->chain(ev);
  }
  void Verilog::Binary::callback(Callback& cb) const
  {
    cb.trap( this );
  }
  ////////////////////////////////////////////////////////////////////////
  // Verilog::Ternary
  ////////////////////////////////////
  Verilog::Ternary::~Ternary()
  {
    delete expr_;
    delete true_;
    delete false_;
  }