verilog.y

将Verilog代码转换成C++代码的软件

{
  $$ =moe::Verilog::Net::SUPPLY1;
}
| K_wor     
{
  $$ =moe::Verilog::Net::WOR;
}
| K_trior   
{
  $$ =moe::Verilog::Net::TRIOR;
}
;



v2k_net_type
: K_reg
{
  $$ =moe::Verilog::Net::REG;
}
| K_wire    
{
  $$ =moe::Verilog::Net::WIRE;
}
| K_tri     
{
  $$ =moe::Verilog::Net::TRI;
}
| K_tri1    
{
  $$ =moe::Verilog::Net::TRI1;
}
| K_supply0 
{
  $$ =moe::Verilog::Net::SUPPLY0;
}
| K_wand    
{
  $$ =moe::Verilog::Net::WAND;
}
| K_triand  
{
  $$ =moe::Verilog::Net::TRIAND;
}
| K_tri0    
{
  $$ =moe::Verilog::Net::TRI0;
}
| K_supply1 
{
  $$ =moe::Verilog::Net::SUPPLY1;
}
| K_wor     
{
  $$ =moe::Verilog::Net::WOR;
}
| K_trior   
{
  $$ =moe::Verilog::Net::TRIOR;
}
;

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////

gate_instance_list
: gate_instance_list ',' gate_instance
| gate_instance
;
gate_instance
: IDENTIFIER '(' expression_list ')'
{
  delete $1;
  delete $3;
}
| '(' expression_list ')'
{
  delete $2;
}
;


/******
port_opt
: port 
{
  $$ =$1;
}
|
{
  $$ =NULL;
}
;

port
: port_reference
{
  $$ =$1;
}
| PORTNAME '(' port_reference ')'
{
  error("not supported.");
  delete $1;
  delete $3;
  $$ =NULL; 
}
| '{' port_reference_list '}'
{
  error("not supported.");
  delete $2;
  $$ =NULL; 
}
| PORTNAME '(' '{' port_reference_list '}' ')'
{
  error("not supported.");
  delete $1;
  delete $4;
  $$ =NULL; 
}
;

port_reference
: IDENTIFIER
{
  $$ =$1;
}
| IDENTIFIER '[' expression ':' expression ']'
{
  error("not supported.");
  delete $1;
  delete $3;
  delete $5;
  $$ =NULL;
}
| IDENTIFIER '[' error ']'
{
  error("error");
}
;

port_reference_list
: port_reference
{
  $$ =$1;
}
| port_reference_list ',' port_reference
{
  error("not supported.");
  delete $1;
  delete $3;
  $$ =NULL;
}
;
******/

block_item_decls_opt
: block_item_decls
{
  $$ =$1;
}
|
{
  $$ =new map<string,moe::Verilog::Net*>;
}
;

block_item_decls
: block_item_decl
{
  map<string,moe::Verilog::Net*>*tmp =new map<string,moe::Verilog::Net*>;
  tmp->insert($1->begin(),$1->end());
  $$ =tmp;
}
| block_item_decls block_item_decl
{
  $1->insert($2->begin(),$2->end());
  $$ =$1;
}
;

block_item_decl
: K_reg range_opt register_variable_list ';'
{
  map<string,moe::Verilog::Net*>* tmp=new map<string,moe::Verilog::Net*>;

  moe::Verilog::Expression* msb;
  moe::Verilog::Expression* lsb;

  list<moe::Verilog::Net::nrm_*>::iterator i;
  for( i=$3->begin();i!=$3->end();++i )
    {
      if( $2!=NULL )
	{
	  msb =(*$2)[0]->clone();
	  lsb =(*$2)[1]->clone();
	}
      else
	{
	  msb =NULL;
	  lsb =NULL;
	}
      
      pair<map<string,moe::Verilog::Net*>::iterator,bool> ret =
	tmp->insert( pair<string,moe::Verilog::Net*>
		     ((*i)->name,new moe::Verilog::Net
		      ((*i)->type,msb,lsb,moe::Verilog::Net::PRIVATE,
		       (((*i)->start!=NULL)?(*i)->start->clone():NULL),
		       (((*i)->end!=NULL)?(*i)->end->clone():NULL))) );
      
      delete *i;
    }
  
  if( $2!=NULL )
    {
      delete (*$2)[0];
      delete (*$2)[1];
      delete $2;
    }
  delete $3;

  $$ =tmp;
}
| K_reg K_signed range_opt register_variable_list ';'
{ // Verilog-2000 enhancements
  map<string,moe::Verilog::Net*>* tmp=new map<string,moe::Verilog::Net*>;

  moe::Verilog::Expression* msb;
  moe::Verilog::Expression* lsb;

  list<moe::Verilog::Net::nrm_*>::iterator i;
  for( i=$4->begin();i!=$4->end();++i )
    {
      if( $3!=NULL )
	{
	  msb =(*$3)[0]->clone();
	  lsb =(*$3)[1]->clone();
	}
      else
	{
	  msb =NULL;
	  lsb =NULL;
	}
      
      pair<map<string,moe::Verilog::Net*>::iterator,bool> ret =
	tmp->insert( pair<string,moe::Verilog::Net*>
		     ((*i)->name,new moe::Verilog::Net
		      ((*i)->type,msb,lsb,moe::Verilog::Net::PRIVATE,
		       (((*i)->start!=NULL)?(*i)->start->clone():NULL),
		       (((*i)->end!=NULL)?(*i)->end->clone():NULL),
		       true)) );
      delete *i;
    }
  
  if( $3!=NULL )
    {
      delete (*$3)[0];
      delete (*$3)[1];
      delete $3;
    }
  delete $4;

  $$ =tmp;
}
| K_integer list_of_variables ';'
{
  map<string,moe::Verilog::Net*>* tmp=new map<string,moe::Verilog::Net*>;

  list<char*>::iterator i;
  for( i=$2->begin();i!=$2->end();++i )
    {
      pair<map<string,moe::Verilog::Net*>::iterator,bool> ret =
	tmp->insert( pair<string,moe::Verilog::Net*>
		     (*i,new moe::Verilog::Net
		      (moe::Verilog::Net::INTEGER,
		       NULL,NULL,moe::Verilog::Net::PRIVATE)) );
      delete *i;
    }
  delete $2;

  $$ =tmp;
}
;




specify_item
: K_specparam specparam_list ';'
| specify_simple_path '=' '(' expression_list ')' ';'
| K_if  '(' expression ')' specify_simple_path '=' '(' expression_list ')' ';'
| SYSTEM_IDENTIFIER '(' timing_check_event ',' timing_check_event ',' expression_list ')' ';'
{
}
;

timing_check_event
: event_expression K_AAA expression
{
}
| event_expression
{
}
;

specify_item_list
: specify_item
| specify_item_list specify_item
;

specify_simple_path
: '(' IDENTIFIER polarity_operator_opt K_EG IDENTIFIER ')'
| '(' IDENTIFIER polarity_operator_opt K_SG IDENTIFIER ')'
| '(' K_posedge IDENTIFIER K_SG '(' IDENTIFIER polarity_operator_opt ':' expression ')' ')'
| '(' K_negedge IDENTIFIER K_SG '(' IDENTIFIER polarity_operator_opt ':' expression ')' ')'
| '(' K_posedge IDENTIFIER K_EG '(' IDENTIFIER polarity_operator_opt ':' expression ')' ')'
| '(' K_negedge IDENTIFIER K_EG '(' IDENTIFIER polarity_operator_opt ':' expression ')' ')'
;

specparam
: IDENTIFIER '=' expression
{
}
;

specparam_list
: specparam
| specparam_list ',' specparam
;

polarity_operator_opt
: '+'
| '-'
|
;





defparam_assign
: identifier '=' expression
{
}
;

defparam_assign_list
: defparam_assign
| range defparam_assign
{
}
| defparam_assign_list ',' defparam_assign
;

event_control
: '@' IDENTIFIER
{
  $$ =0;
}
| '@' '(' event_expression_list ')'
{
  moe::Verilog::EventStatement* tmp = new moe::Verilog::EventStatement(*$3);
  delete $3;
  $$ = tmp;
}
| '@' '*'
{ // Verilog-2000 enhancements
  moe::Verilog::EventStatement* tmp = new moe::Verilog::EventStatement();
  $$ = tmp;
}
| '@' '(' error ')'
{
  $$ =0;
}
;

task_body
: task_item_list_opt statement_opt
{
}
;

task_item
: K_reg range register_variable_list ';'
{
}
| K_reg register_variable_list ';'
{
}
| K_integer list_of_variables ';'
{
}
| K_input range_opt list_of_variables ';'
{
}
| K_output range_opt list_of_variables ';'
{
}
| K_inout range_opt list_of_variables ';'
{
}
;

task_item_list_opt
: task_item_list
|
;

task_item_list
: task_item_list task_item
| task_item
;

////////////////////////////////////////////////////////////////////////

udp_body
: K_table
{
  lex_start_table();
}
udp_entry_list
K_endtable
{
  lex_end_table();
}
;

udp_entry_list
: udp_comb_entry_list
| udp_sequ_entry_list
;

udp_comb_entry
: udp_input_list ':' udp_output_sym ';'
;

udp_comb_entry_list
: udp_comb_entry
| udp_comb_entry_list udp_comb_entry
;

udp_sequ_entry_list
: udp_sequ_entry
| udp_sequ_entry_list udp_sequ_entry
;

udp_sequ_entry
: udp_input_list ':' udp_input_sym ':' udp_output_sym ';'
;

udp_initial
: K_initial IDENTIFIER '=' NUMBER ';'
{
  delete $2;
  delete $4;
}
;

udp_init_opt
: udp_initial
|
;

udp_input_list
: udp_input_sym
| udp_input_list udp_input_sym
;

udp_input_sym
: '0'
| '1'
| 'x'
| '?'
| 'b'
| '*'
| 'f'
| 'r'
| 'n'
| 'p'
| '_'
| '+'
| '%'
| 'P'
| 'N'
| 'F'
| 'R'
;

udp_output_sym
: '0'
| '1'
| 'x'
| '-'
;

udp_port_decl
: K_input list_of_variables ';'
{
  list<char*>::iterator i;
  for( i=$2->begin();i!=$2->end();++i )
    delete *i;
  delete $2;
}
| K_output IDENTIFIER ';'
{
  delete $2;
}
| K_reg IDENTIFIER ';'
{
  delete $2;
}
;

udp_primitive
: K_primitive IDENTIFIER '(' udp_port_list ')' ';'
{
  delete $2;
}
udp_port_decls
udp_init_opt
udp_body
K_endprimitive
;

udp_port_list
: IDENTIFIER
{
  delete $1;
}
| udp_port_list ',' IDENTIFIER
{
  delete $3;
}
;

udp_port_decls
: udp_port_decl
| udp_port_decls udp_port_decl
;


////////////////////////////////////////////////////////////////////////
attribute_instance_opt
: K_ATCOMM
{
  $$ =(char*)verilog_comment.c_str();
}
|
{
  $$ =NULL;  
}
;

parameter_value_opt
: '#' '(' expression_list ')'
{
  delete $3;
}
| '#' '(' parameter_value_byname_list ')'
| '#' NUMBER
{
  delete $2;
}
| '#' REALTIME
{
  delete $2;
}
| '#' error
|
;

//  Verilog-2000 enhancements
parameter_value_byname_list
: parameter_value_byname
| parameter_value_byname_list ',' parameter_value_byname
;

parameter_value_byname
: PORTNAME '(' expression ')'
{
  delete $1;
  delete $3;
}
| PORTNAME '(' ')'
{
  delete $1;
}
;

delay1
: '#' delay_value_simple
| '#' '(' delay_value ')'
;

delay3_opt
: delay3
|
;

delay3
: '#' delay_value_simple
| '#' '(' delay_value ')'
| '#' '(' delay_value ',' delay_value ')'
| '#' '(' delay_value ',' delay_value ',' delay_value ')'
;

delay_value
: expression
{
  delete $1;
}
| expression ':' expression ':' expression
{
  delete $1;
  delete $3;
  delete $5;
}
;

delay_value_simple
: NUMBER
{
  delete $1;
}
| IDENTIFIER
{
  delete $1;
}
;

drive_strength
: '(' dr_strength0 ',' dr_strength1 ')'
| '(' dr_strength1 ',' dr_strength0 ')'
| '(' dr_strength0 ',' K_highz1 ')'
| '(' dr_strength1 ',' K_highz0 ')'
| '(' K_highz1 ',' dr_strength0 ')'
| '(' K_highz0 ',' dr_strength1 ')'
;

drive_strength_opt
: drive_strength
|
;

dr_strength0
: K_supply0
| K_strong0
| K_pull0
| K_weak0
;

dr_strength1
: K_supply1
| K_strong1
| K_pull1
| K_weak1
;

charge_strength_opt
: charge_strength
|
;

charge_strength
: '(' K_small ')'
| '(' K_medium ')'
| '(' K_large ')'
;

////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////

%%

void verilog_error(char *str)
{
  cerr << file << " : " << line << " : " << str << endl;
}