verilog.y

将Verilog代码转换成C++代码的软件

      lsb =(*$2)[1]->clone();
      
      delete (*$2)[0];
      delete (*$2)[1];
      delete $2;
    }

  module_->newNet($3,moe::Verilog::Net::IMPLICIT,
		  msb,lsb,
		  $1 );
  module_->addPort( $3 );

  delete $3;
}
| port_type v2k_net_type range_opt IDENTIFIER
{
  moe::Verilog::Expression* msb=NULL;
  moe::Verilog::Expression* lsb=NULL;
  if( $3!=NULL )
    {
      msb =(*$3)[0]->clone();
      lsb =(*$3)[1]->clone();
      
      delete (*$3)[0];
      delete (*$3)[1];
      delete $3;
    }

  module_->newNet($4,$2,
		  msb,lsb,
		  $1);
  module_->addPort( $4 );

  delete $4;
}
| port_type K_signed v2k_net_type range_opt IDENTIFIER
{ // Verilog-2001 enhancements
  moe::Verilog::Expression* msb=NULL;
  moe::Verilog::Expression* lsb=NULL;
  if( $4!=NULL )
    {
      msb =(*$4)[0]->clone();
      lsb =(*$4)[1]->clone();
      
      delete (*$4)[0];
      delete (*$4)[1];
      delete $4;
    }

  module_->newNet($5,$3,
		  msb,lsb,
		  $1,
		  NULL,NULL,
		  true);
  module_->addPort( $5 );

  delete $5;
}
;

port_opt
: IDENTIFIER
{
  module_->addPort( $1 );
  delete $1;
}
| v2k_port_item
;

list_of_ports
: port_opt
| list_of_ports ',' port_opt
;

list_of_ports_opt
: '(' list_of_ports ')'
| '(' ')'
|
;

list_of_variables
: IDENTIFIER
{
  list<char*>* tmp =new list<char*>;
  tmp->push_back($1);
  $$ =tmp;
}
| list_of_variables ',' IDENTIFIER
{
  $1->push_back($3);
  $$ =$1;
}
;

lavalue
: identifier
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression ']'
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,NULL,NULL,$3);
  delete $1;
  $$ = tmp;
}
| identifier range
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,(*$2)[0],(*$2)[1]);
  delete $1;
  delete $2;
  $$ = tmp;
}
| '{' expression_list '}'
{
  moe::Verilog::Concat* tmp = new moe::Verilog::Concat(*$2);
  delete $2;
  $$ = tmp;
}
;

lpvalue
: identifier
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression ']'
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,NULL,NULL,$3);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression ':' expression ']'
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,$3,$5);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression K_PLUSRANGE expression ']'
{ // Verilog-2000 enhancements
  moe::Verilog::Expression* msb =new moe::Verilog::Binary
    (
     moe::Verilog::Expression::ArithmeticMinus,
     (new moe::Verilog::Binary
      (
       moe::Verilog::Expression::ArithmeticAdd,$3,$5
       )
      ),
     (new moe::Verilog::Number("1"))
     );
  moe::Verilog::Expression* lsb =($3)->clone();

  moe::Verilog::Identifier* tmp =new moe::Verilog::Identifier($1,msb,lsb);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression K_MINUSRANGE expression ']'
{ // Verilog-2000 enhancements
  moe::Verilog::Expression* lsb =new moe::Verilog::Binary
    (
     moe::Verilog::Expression::ArithmeticAdd,
     new moe::Verilog::Binary
     (
      moe::Verilog::Expression::ArithmeticMinus,$3,$5
      ),
     new moe::Verilog::Number("1")
     );
  moe::Verilog::Expression* msb =($3)->clone();

  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,msb,lsb);
  delete $1;
  $$ = tmp;
}
| '{' expression_list '}'
{
  moe::Verilog::Concat* tmp = new moe::Verilog::Concat(*$2);
  delete $2;
  $$ = tmp;
}
;

net_decl_assign
: IDENTIFIER '=' expression
{
  module_->addAssign( new moe::Verilog::Identifier($1),$3 );
  $$ =$1;
}
| delay1 IDENTIFIER '=' expression
{
  module_->addAssign( new moe::Verilog::Identifier($2),$4 );
  $$ =$2;
}
;

net_decl_assigns
: net_decl_assigns ',' net_decl_assign
{
  $1->push_back($3);
  $$ =$1;
}
| net_decl_assign
{
  list<char*>*tmp =new list<char*>;
  tmp->push_back($1);
  $$ =tmp;
}
;

parameter_assign_list
: parameter_assign
| parameter_assign_list ',' parameter_assign
;
parameter_assign
: range_opt IDENTIFIER '=' expression
{
  moe::Verilog::Expression* msb=NULL;
  moe::Verilog::Expression* lsb=NULL;
  if( $1!=NULL )
    {
      msb =(*$1)[0]->clone();
      lsb =(*$1)[1]->clone();
      
      delete (*$1)[0];
      delete (*$1)[1];
      delete $1;
    }

  module_->newNet($2,moe::Verilog::Net::PARAMETER,msb,lsb,
		  moe::Verilog::Net::PRIVATE );
  module_->addParameter( new moe::Verilog::Identifier($2),$4 );

  delete $2;
}
;

range
: '[' expression ':' expression ']'
{
  vector<moe::Verilog::Expression*>*tmp = new vector<moe::Verilog::Expression*>(2);
  (*tmp)[0] = $2;
  (*tmp)[1] = $4;
  $$ = tmp;
}
| '[' expression K_PLUSRANGE expression ']'
{ // Verilog-2000 enhancements
  vector<moe::Verilog::Expression*>*tmp = new vector<moe::Verilog::Expression*>(2);
  (*tmp)[0] = new moe::Verilog::Binary
    (
     moe::Verilog::Expression::ArithmeticMinus,
     new moe::Verilog::Binary
     (
      moe::Verilog::Expression::ArithmeticAdd, $2,$4 ),
     new moe::Verilog::Number("1") ) ;
  (*tmp)[1] = ($2)->clone();
  $$ = tmp;
}
| '[' expression K_MINUSRANGE expression ']'
{ // Verilog-2000 enhancements
  vector<moe::Verilog::Expression*>*tmp = new vector<moe::Verilog::Expression*>(2);
  (*tmp)[0] = ($2)->clone();
  (*tmp)[1] = new moe::Verilog::Binary
    (
     moe::Verilog::Expression::ArithmeticAdd,
     new moe::Verilog::Binary
     (
      moe::Verilog::Expression::ArithmeticMinus, $2,$4 ),
     new moe::Verilog::Number("1") ) ;
  $$ = tmp;
}
;

range_opt
: range
|
{
  $$ =0;
}
;

range_or_type_opt
: range 
{
  $$ =$1;
}
| K_integer
{
  $$ =NULL;
}
| K_real
{
  $$ =NULL;
}
|
{
  $$ =NULL;
}
;

register_variable_list
: register_variable
{
  list<moe::Verilog::Net::nrm_*>* tmp =new list<moe::Verilog::Net::nrm_*>;
  tmp->push_back($1);
  $$ =tmp;
 
}
| register_variable_list ',' register_variable
{
  $1->push_back($3);
  $$ =$1;
}
;
register_variable
: IDENTIFIER
{
  moe::Verilog::Net::nrm_* tmp =new moe::Verilog::Net::nrm_;
  tmp->name  =$1;
  tmp->start =NULL;
  tmp->end   =NULL;
  tmp->type  =moe::Verilog::Net::REG;
  $$ =tmp;
}
| IDENTIFIER '[' expression ':' expression ']'
{
  moe::Verilog::Net::nrm_* tmp =new moe::Verilog::Net::nrm_;
  tmp->name  =$1;
  tmp->start =$3;
  tmp->end   =$5;
  tmp->type  =moe::Verilog::Net::REG;
  $$ =tmp;
}
;

expression
: expr_primary
{
  $$ = $1;
}
| '+' expr_primary %prec UNARY_PREC
{
  $$ = $2;
}
| '-' expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ArithmeticMinus,$2);
  $$ = tmp;
}
| '~' expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::BitwiseNegation,$2);
  $$ = tmp;
}
| '&' expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionAND,$2);
  $$ = tmp;
}
| '!' expr_primary %prec UNARY_PREC
{
    moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::LogicalNegation,$2);
  $$ = tmp;
}
| '|' expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionOR,$2);
  $$ = tmp;
}
| '^' expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionXOR,$2);
  $$ = tmp;
}
| K_NAND expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionNAND,$2);
  $$ = tmp;
}
| K_NOR expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionNOR,$2);
  $$ = tmp;
}
| K_NXOR expr_primary %prec UNARY_PREC
{
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::ReductionNXOR,$2);
  $$ = tmp;
}
| expression '^' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::BitwiseXOR,$1,$3);
  $$ = tmp;
}
| expression '*' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticMultiply,$1,$3);
  $$ = tmp;
}
| expression '/' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticDivide,$1,$3);
  $$ = tmp;
}
| expression '%' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticModulus,$1,$3);
  $$ = tmp;
}
| expression '+' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticAdd,$1,$3);
  $$ = tmp;
}
| expression '-' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticMinus,$1,$3);
  $$ = tmp;
}
| expression '&' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::BitwiseAND,$1,$3);
  $$ = tmp;
}
| expression '|' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::BitwiseOR,$1,$3);
  $$ = tmp;
}
| expression K_NOR expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::BitwiseNOR,$1,$3);
  $$ = tmp;
}
| expression K_NXOR expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::BitwiseNXOR,$1,$3);
  $$ = tmp;
}
| expression '<' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LessThan,$1,$3);
  $$ = tmp;
}
| expression '>' expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::GreaterThan,$1,$3);
  $$ = tmp;
}
| expression K_LS expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LeftShift,$1,$3);
  $$ = tmp;
}
| expression K_RS expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::RightShift,$1,$3);
  $$ = tmp;
}
| expression K_ALS expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticLeftShift,$1,$3);
  $$ = tmp;
}
| expression K_ARS expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticRightShift,$1,$3);
  $$ = tmp;
}
| expression K_POW expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::ArithmeticPower,$1,$3);
  $$ = tmp;
}
| expression K_EQ expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LogicalEquality,$1,$3);
  $$ = tmp;
}
| expression K_CEQ expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::CaseEquality,$1,$3);
  $$ = tmp;
}
| expression K_LE expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LessEqual,$1,$3);
  $$ = tmp;
}
| expression K_GE expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::GreaterEqual,$1,$3);
  $$ = tmp;
}
| expression K_NE expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LogicalInequality,$1,$3);
  $$ = tmp;
}
| expression K_CNE expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::CaseInequality,$1,$3);
  $$ = tmp;
}
| expression K_LOR expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LogicalOR,$1,$3);
  $$ = tmp;
}
| expression K_LAND expression
{
  moe::Verilog::Binary* tmp = new moe::Verilog::Binary( moe::Verilog::Expression::LogicalAND,$1,$3);
  $$ = tmp;
}
| expression '?' expression ':' expression
{
  moe::Verilog::Ternary* tmp = new moe::Verilog::Ternary($1,$3,$5);
  $$ = tmp;
}
| K_SIGNED '(' expression ')'
{ // Verilog-2000 enhancements
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::CastSigned,$3);
  $$ = tmp;
}
| K_UNSIGNED '(' expression ')'
{ // Verilog-2000 enhancements
  moe::Verilog::Unary* tmp = new moe::Verilog::Unary( moe::Verilog::Expression::CastUnsigned,$3);
  $$ = tmp;
}
;

gatetype
: K_and  
{
  $$ =moe::Verilog::Gate::AND;
}
| K_nand 
{
  $$ =moe::Verilog::Gate::NAND;
}
| K_or   
{
  $$ =moe::Verilog::Gate::OR;
}
| K_nor  
{
  $$ =moe::Verilog::Gate::NOR;
}
| K_xor  
{
  $$ =moe::Verilog::Gate::XOR;
}
| K_xnor 
{
  $$ =moe::Verilog::Gate::XNOR;
}
| K_buf  
{
  $$ =moe::Verilog::Gate::BUF;
}
| K_bufif0 
{
  $$ =moe::Verilog::Gate::BUFIF0;
}
| K_bufif1 
{
  $$ =moe::Verilog::Gate::BUFIF1;
}
| K_not    
{
  $$ =moe::Verilog::Gate::NOT;
}
| K_notif0 
{
  $$ =moe::Verilog::Gate::NOTIF0;
}
| K_notif1 
{
  $$ =moe::Verilog::Gate::NOTIF1;
}
| K_pulldown 
{
  $$ =moe::Verilog::Gate::PULLDOWN;
}
| K_pullup   
{
  $$ =moe::Verilog::Gate::PULLUP;
}
| K_nmos  
{
  $$ =moe::Verilog::Gate::NMOS;
}
| K_rnmos 
{
  $$ =moe::Verilog::Gate::RNMOS;
}
| K_pmos  
{
  $$ =moe::Verilog::Gate::PMOS;
}
| K_rpmos 
{
  $$ =moe::Verilog::Gate::RPMOS;
}
| K_cmos  
{
  $$ =moe::Verilog::Gate::CMOS;
}
| K_rcmos 
{
  $$ =moe::Verilog::Gate::RCMOS;
}
| K_tran  
{
  $$ =moe::Verilog::Gate::TRAN;
}
| K_rtran 
{
  $$ =moe::Verilog::Gate::RTRAN;
}
| K_tranif0 
{
  $$ =moe::Verilog::Gate::TRANIF0;
}
| K_tranif1 
{
  $$ =moe::Verilog::Gate::TRANIF1;
}
| K_rtranif0 
{
  $$ =moe::Verilog::Gate::RTRANIF0;
}
| K_rtranif1 
{
  $$ =moe::Verilog::Gate::RTRANIF1;
}
;

port_type
: K_input 
{
  $$ =moe::Verilog::Net::INPUT;
}
| K_output
{
  $$ =moe::Verilog::Net::OUTPUT;
}
| K_inout
{
  $$ =moe::Verilog::Net::INOUT;
}
;

net_type
: K_wire    
{
  $$ =moe::Verilog::Net::WIRE;
}
| K_tri     
{
  $$ =moe::Verilog::Net::TRI;
}
| K_tri1    
{
  $$ =moe::Verilog::Net::TRI1;
}
| K_supply0 
{
  $$ =moe::Verilog::Net::SUPPLY0;
}
| K_wand    
{
  $$ =moe::Verilog::Net::WAND;
}
| K_triand  
{
  $$ =moe::Verilog::Net::TRIAND;
}
| K_tri0    
{
  $$ =moe::Verilog::Net::TRI0;
}
| K_supply1