verilog.y

将Verilog代码转换成C++代码的软件

  for( i=$4->begin();i!=$4->end();++i )
    if( *i!=NULL )
      (*i)->setType($1);
  delete $1;
  delete $4;
}
| K_always statement
{
  moe::Verilog::Process* proc =new moe::Verilog::Process(moe::Verilog::Process::ALWAYS,$2);
  module_->addProcess( proc );
}
| K_function range_or_type_opt IDENTIFIER ';'
{
  moe::Verilog::Expression* msb=NULL;
  moe::Verilog::Expression* lsb=NULL;
  if( $2!=NULL )
    {
      msb =(*$2)[0]->clone();
      lsb =(*$2)[1]->clone();
      
      delete (*$2)[0];
      delete (*$2)[1];
      delete $2;
    }

  function_ =module_->newFunction($3);
  moe::Verilog::Net* net =new
    moe::Verilog::Net(moe::Verilog::Net::FUNCTION,
		      msb,lsb,moe::Verilog::Net::OUTPUT);
  function_->addNet($3,net);

  delete $3;
}
func_body K_endfunction
////////////////////////////////////////////////////////////////////////
| K_defparam defparam_assign_list ';'
{
}
| K_event list_of_variables ';'
{
  list<char*>::iterator i;
  for( i=$2->begin();i!=$2->end();++i )
    delete *i;
  delete $2;
}
| K_initial statement
{
  error("not supported.");
}
| K_task IDENTIFIER ';' task_body K_endtask
{
  error("not supported.");
  delete $2;
}
| K_specify specify_item_list K_endspecify
{
  error("not supported.");
}
| K_D_attribute '(' IDENTIFIER ',' STRING ',' STRING ')' ';'
{
  error("not supported.");
  delete $3;
  delete $5;
  delete $7;
}
| K_D_attribute '(' error ')' ';'
{
  error("not supported.");
}
| K_trireg charge_strength_opt range_opt delay3_opt list_of_variables ';'
{
  if( $3!=NULL )
    {
      delete (*$3)[0];
      delete (*$3)[1];
      delete $3;
    }
  list<char*>::iterator i;
  for( i=$5->begin();i!=$5->end();++i )
    delete *i;
  delete $5;
}
| gatetype gate_instance_list ';'
{
}
| gatetype drive_strength gate_instance_list ';'
{
}
| gatetype delay3 gate_instance_list ';'
{
}
| gatetype drive_strength delay3 gate_instance_list ';'
{
}
| K_assign error '=' expression ';'
;

assign_list
: assign_list ',' assign
| assign
;

assign
: lavalue '=' expression
{
  module_->addAssign( $1,$3 );
}
;

statement_opt
: statement
| ';'
{
  $$ =NULL;
}
;

statement_list
: statement_list statement
{
  $1->push_back($2);
  $$ =$1;
}
| statement
{
  vector<moe::Verilog::Statement*>*tmp = new vector<moe::Verilog::Statement*>;
  tmp->push_back($1);
  $$ = tmp;
}
;

statement
: K_begin statement_list K_end
{
  moe::Verilog::Block* tmp =new moe::Verilog::Block(moe::Verilog::Block::SEQUENTIAL,*$2);
  delete $2;
  $$ = tmp;
}
| K_begin K_end
{
  moe::Verilog::Block* tmp =new moe::Verilog::Block(moe::Verilog::Block::SEQUENTIAL);
  $$ = tmp;
}
| K_case '(' expression ')' case_items K_endcase
{
  moe::Verilog::Case* tmp =new moe::Verilog::Case(moe::Verilog::Case::CASE, $3,*$5);
  delete $5;
  $$ = tmp;
}
| K_casex '(' expression ')' case_items K_endcase
{
  moe::Verilog::Case* tmp =new moe::Verilog::Case(moe::Verilog::Case::CASEX, $3,*$5);
  delete $5;
  $$ = tmp;
}
| K_casez '(' expression ')' case_items K_endcase
{
  moe::Verilog::Case* tmp =new moe::Verilog::Case(moe::Verilog::Case::CASEZ, $3,*$5);
  delete $5;
  $$ = tmp;
}
| K_if '(' expression ')' statement_opt %prec less_than_K_else
{
  moe::Verilog::Condition* tmp =new moe::Verilog::Condition($3,$5,NULL);
  $$ = tmp;
}
| K_if '(' expression ')' statement_opt K_else statement_opt
{
  moe::Verilog::Condition* tmp =new moe::Verilog::Condition($3,$5,$7);
  $$ = tmp;
}
| lpvalue '=' expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::BLOCKING,$1,$3);
  $$ = tmp;
}
| lpvalue K_LE expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::NONBLOCKING,$1,$3);
  $$ = tmp;
}
| lpvalue '=' delay1 expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::BLOCKING,$1,$4);
  $$ = tmp;
}
| lpvalue K_LE delay1 expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::NONBLOCKING,$1,$4);
  $$ =tmp;
}
| lpvalue '=' DIDENTIFIER expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::BLOCKING,$1,$4);
  $$ = tmp;
}
| lpvalue K_LE DIDENTIFIER expression ';'
{
  moe::Verilog::Assign* tmp =new moe::Verilog::Assign(moe::Verilog::Assign::NONBLOCKING,$1,$4);
  $$ =tmp;
}
| event_control statement_opt
{
  $1->setStatement($2);
  $$ =$1;
}
////////////////////////////////////////////////////////////////////////
| K_begin ':' IDENTIFIER block_item_decls_opt statement_list K_end
{
  moe::Verilog::Block* tmp =new moe::Verilog::Block(moe::Verilog::Block::SEQUENTIAL,*$5,$3,*$4);
  {
    map<string,moe::Verilog::Net*>::const_iterator i;
    for( i=(*$4).begin();i!=(*$4).end();++i )
      {
	string aname =string(".") + string($3) + string(".") + i->first;
	//cout << aname << "\n";
       	module_->addNet( aname.c_str() ,i->second );
	i->second->setType(moe::Verilog::Net::HIDDEN);
      }
  }
  delete $5;
  delete $4;
  $$ = tmp;
}
| K_begin ':' IDENTIFIER K_end
{
}
| K_assign lavalue '=' expression ';'
{
}
| K_deassign lavalue';'
{ 
}
| K_disable IDENTIFIER ';'
{
}
| K_force lavalue '=' expression ';'
{
}
| K_TRIGGER IDENTIFIER ';'
{
}
| K_forever statement
{
}
| K_fork statement_list K_join
{
}
| K_fork ':' IDENTIFIER block_item_decls_opt statement_list K_join
{
}
| K_fork K_join
{
}
| K_fork ':' IDENTIFIER K_join
{
}
| K_release lavalue ';'
{
}
| K_repeat '(' expression ')' statement
{
}
| K_for '(' lpvalue '=' expression ';' expression ';' lpvalue '=' expression ')' statement
{
  moe::Verilog::For* tmp =new moe::Verilog::For((moe::Verilog::Identifier*)$3,$5,
						$7,
						(moe::Verilog::Identifier*)$9,$11,
						$13);
  $$ = tmp;
}
| K_while '(' expression ')' statement
{
}
| delay1 statement_opt
{
}
| lpvalue '=' event_control expression ';'
{
}
| lpvalue '=' K_repeat '(' expression ')' event_control expression ';'
{
}
| lpvalue K_LE event_control expression ';'
{
}
| lpvalue K_LE K_repeat '(' expression ')' event_control expression ';'
{
}
| K_wait '(' expression ')' statement_opt
{
}
| SYSTEM_IDENTIFIER '(' expression_list ')' ';'
{

}
| SYSTEM_IDENTIFIER '(' ')' ';'
{

}
| SYSTEM_IDENTIFIER ';'
{
  
}
| identifier '(' expression_list ')' ';'
{
}
| identifier '(' ')' ';'
{
}
| identifier ';'
{
}
| error ';'
{
}
| K_begin error K_end
{ yyerrok; }
| K_case '(' expression ')' error K_endcase
{ yyerrok; }
| K_casex '(' expression ')' error K_endcase
{ yyerrok; }
| K_casez '(' expression ')' error K_endcase
{ yyerrok; }
| K_if '(' error ')' statement_opt %prec less_than_K_else
{ yyerrok; }
| K_if '(' error ')' statement_opt K_else statement_opt
{ yyerrok; }
| K_for '(' error ')' statement
{ yyerrok; }
| K_while '(' error ')' statement
{ yyerrok; }
| K_for '(' lpvalue '=' expression ';' expression ';' error ')' statement
{ yyerrok; }
| K_for '(' lpvalue '=' expression ';' error ';' lpvalue '=' expression ')' statement
{ yyerrok; }
;

case_items
: case_items case_item
{
  $1->push_back($2);
  $$ =$1;
}
| case_item
{
  vector<moe::Verilog::Case::Item*>*tmp = new vector<moe::Verilog::Case::Item*>;
  tmp->push_back($1);
  $$ = tmp;
}
;

case_item
: expression_list ':' statement_opt
{
  moe::Verilog::Case::Item* tmp = new moe::Verilog::Case::Item(*$1,$3);
  delete $1;
  $$ = tmp;
}
| K_default ':' statement_opt
{
  moe::Verilog::Case::Item*tmp = new moe::Verilog::Case::Item($3);
  $$ = tmp;
}
| K_default  statement_opt
{
  moe::Verilog::Case::Item*tmp = new moe::Verilog::Case::Item($2);
  $$ = tmp;
}
| error ':' statement_opt
{
  yyerrok;
}
;

event_expression_list
: event_expression
{
  vector<moe::Verilog::Event*>*tmp = new vector<moe::Verilog::Event*>;
  tmp->push_back($1);
  $$ = tmp;
}
| event_expression_list K_or event_expression
{
  $1->push_back($3);
  $$ =$1;
}
| event_expression_list ',' event_expression
{ // Verilog-2000 enhancements
  $1->push_back($3);
  $$ =$1;
}
;

event_expression
: K_posedge expression
{
  moe::Verilog::Event* tmp = new moe::Verilog::Event(moe::Verilog::Event::POSEDGE,$2);
  $$ = tmp;
}
| K_negedge expression
{
  moe::Verilog::Event* tmp = new moe::Verilog::Event(moe::Verilog::Event::NEGEDGE,$2);
  $$ = tmp;
}
| expression
{
  moe::Verilog::Event* tmp = new moe::Verilog::Event(moe::Verilog::Event::ANYEDGE,$1);
  $$ = tmp;
}
;

expression_list
: expression_list ',' expression
{
  $1->push_back($3);
  $$ =$1;
}
| expression
{
  vector<moe::Verilog::Expression*>*tmp = new vector<moe::Verilog::Expression*>;
  tmp->push_back($1);
  $$ = tmp;
}
| expression_list ','
{
  $$ = $1;
}
;

expr_primary
: NUMBER
{
  moe::Verilog::Number* tmp = new moe::Verilog::Number($1);
  delete $1;
  $$ = tmp;
}
| REALTIME
{
  error("not supported.");
  delete $1;
  $$ = 0;
}
| STRING
{
  error("not supported.");
  delete $1;
  $$ = 0;
}
| identifier
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1);
  delete $1;
  $$ = tmp;
}
| SYSTEM_IDENTIFIER
{
  error("not supported.");
  delete $1;
  $$ = 0;
}
| identifier '[' expression ']'
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,NULL,NULL,$3);
  delete $1;
  $$ = tmp;
}
| identifier '[' expression ':' expression ']'
{
  moe::Verilog::Identifier* tmp = new moe::Verilog::Identifier($1,$3,$5);
  delete $1;
  $$ = tmp;
}
| identifier '(' expression_list ')'
{
  moe::Verilog::CallFunction* tmp = new moe::Verilog::CallFunction($1,*$3);
  $$ = tmp;
}
| SYSTEM_IDENTIFIER '(' expression_list ')'
{
  error("not supported.");
  delete $1;
  $$ = 0;
}
| '(' expression ')'
{
  $$ = $2;
}
| '{' expression_list '}'
{
  moe::Verilog::Concat* tmp = new moe::Verilog::Concat(*$2);
  delete $2;
  $$ = tmp;
}
| '{' expression '{' expression_list '}' '}'
{
  moe::Verilog::Concat* tmp = new moe::Verilog::Concat($2,*$4);
  delete $4;
  $$ = tmp;
}
;

func_body
: function_item_list statement
{
  function_->setStatement($2);
}
| function_item_list
;

function_item_list
: function_item
| function_item_list function_item
;

function_item
: K_input range_opt list_of_variables ';'
{
  moe::Verilog::Expression* msb;
  moe::Verilog::Expression* lsb;

  list<char*>::iterator i;
  for( i=$3->begin();i!=$3->end();++i )
    {
      if( $2!=NULL )
	{
	  msb =(*$2)[0]->clone();
	  lsb =(*$2)[1]->clone();
	}
      else
	{
	  msb =NULL;
	  lsb =NULL;
	}

      function_->addNet(*i,new moe::Verilog::Net
			(moe::Verilog::Net::IMPLICIT,
			 msb,lsb,moe::Verilog::Net::INPUT) );
      delete *i;
    }

  if( $2!=NULL )
    {
      delete (*$2)[0];
      delete (*$2)[1];
      delete $2;
    }
  delete $3;
}
| K_reg range_opt register_variable_list ';'
{
  moe::Verilog::Expression* msb;
  moe::Verilog::Expression* lsb;

  list<moe::Verilog::Net::nrm_*>::iterator i;
  for( i=$3->begin();i!=$3->end();++i )
    {
      if( $2!=NULL )
	{
	  msb =(*$2)[0]->clone();
	  lsb =(*$2)[1]->clone();
	}
      else
	{
	  msb =NULL;
	  lsb =NULL;
	}

      function_->addNet((*i)->name,new moe::Verilog::Net
			((*i)->type,msb,lsb,moe::Verilog::Net::PRIVATE,
			 (((*i)->start!=NULL)?(*i)->start->clone():NULL),
			 (((*i)->end!=NULL)?(*i)->end->clone():NULL)));
      delete *i;
    }

  if( $2!=NULL )
    {
      delete (*$2)[0];
      delete (*$2)[1];
      delete $2;
    }
  delete $3;
}
| K_integer list_of_variables ';'
{
  list<char*>::iterator i;
  for( i=$2->begin();i!=$2->end();++i )
    {
      function_->addNet(*i,new moe::Verilog::Net
			(moe::Verilog::Net::INTEGER,
			 NULL,NULL,moe::Verilog::Net::PRIVATE));
      delete *i;
    }
  delete $2;
}
;

module_instance_list
: module_instance_list ',' module_instance
{
  $1->push_back($3);
  $$ =$1;
}
| module_instance
{
  vector<moe::Verilog::Instance*>*tmp = new vector<moe::Verilog::Instance*>;
  tmp->push_back($1);
  $$ = tmp;
}
;

module_instance
: IDENTIFIER
{
  instance_ =module_->newInstance($1);
  delete $1;
}
'(' port_name_list ')'
{
  $$ =instance_;
}
| '(' expression_list ')' // UDP_instance
{
  delete $2;
  $$ =NULL;
}
;

port_name_list
: port_name_list ',' port_name
| port_name
;

port_name
: PORTNAME '(' expression ')'
{
  moe::Verilog::Instance::Port* port =new moe::Verilog::Instance::Port($1,$3);
  instance_->addPort( port );
}
| PORTNAME '(' ')'
{
  moe::Verilog::Instance::Port* port =new moe::Verilog::Instance::Port($1,NULL);
  instance_->addPort( port );
}
| PORTNAME '(' error ')'
{
  moe::Verilog::Instance::Port* port =new moe::Verilog::Instance::Port($1,NULL);
  instance_->addPort( port );
}
| expression
{
  moe::Verilog::Instance::Port* port =new moe::Verilog::Instance::Port("",$1);
  instance_->addPort( port );
}
|
{
}
;


identifier
: IDENTIFIER
{
  $$ =$1;
}
| HIDENTIFIER
{
  $$ =$1;
}
| DIDENTIFIER
{
  $$ =$1;
}
;

// Verilog-2000 enhancements
v2k_port_item
: port_type range_opt IDENTIFIER
{
  moe::Verilog::Expression* msb=NULL;
  moe::Verilog::Expression* lsb=NULL;
  if( $2!=NULL )
    {
      msb =(*$2)[0]->clone();