verilog.hh

将Verilog代码转换成C++代码的软件

	SUPPLY0,
	WAND,
	TRIAND,
	TRI0,
	SUPPLY1,
	WOR, 
	TRIOR,
	REG,
	INTEGER,
	REAL,
	PARAMETER,
	FUNCTION,
	DEFINE,
	CONSTANT,

	HIDDEN
      };
      enum
      {
	PRIVATE,
	INPUT,
	OUTPUT,
	INOUT
      };
      enum
      {
	UNSIGNED,
	SIGNED
      };

      Net(int type,Expression* msb=NULL,Expression* lsb=NULL,
	  int inter=PRIVATE,Expression* sa=NULL,Expression* ea=NULL,
	  bool sign=false):
	type_(type),
	msb_(msb),
	lsb_(lsb),
	interface_(inter),
	sa_(sa),
	ea_(ea),
	sign_(sign)
      {}
      Net(){}
      virtual ~Net(){}
      void setInterface(int p) { interface_=p; }
      int interface() const { return interface_; }
      void setType(int t) { type_=t; }
      int type() const { return type_; }
      bool sign() const { return sign_; }

      const string& name() const { return name_; }

      const Expression* msb() const { return msb_; }
      const Expression* lsb() const { return lsb_; }
      const Expression* sa() const { return sa_; }
      const Expression* ea() const { return ea_; }
      
      bool isArray() const
      {
	if( (sa_!=NULL)&&(ea_!=NULL) )
	  return true;
	else
	  return false;
      }

      unsigned int depth() const
      {
	if( (sa_!=NULL)&&(ea_!=NULL) )
	  return (ea_->calcConstant()-sa_->calcConstant()+1);
	else
	  return 0;
      }
      unsigned int width() const
      {
	if( (msb_!=NULL)&&(lsb_!=NULL) )
	  return (msb_->calcConstant()-lsb_->calcConstant()+1);
	else
	  if( (type_==INTEGER)||(type_==PARAMETER) )
	    return 32;
	  else
	    return 1;
      }

      void toXML(std::ostream& ostr,const string& name,int indent=0) const;
      void toVerilog(std::ostream& ostr,const string& name,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Net* clone(const string& hname) const;
      Net* clone() const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Statement
    {
    public:
      Statement(){}
      virtual ~Statement(){}

      virtual void toXML(std::ostream& ostr,int indent=0) const {}
      virtual void toVerilog(std::ostream& ostr,int indent=0) const {}

      virtual void link(const map<string,Net*>& net,Module* mod) {}
      virtual Statement* clone(const string& hname) const { return NULL; }

      virtual void chain(set<const Statement*>& ss) const {}

      virtual void callback(Callback& cb) const{}
    };
    ////////////////////////////////////////////////////////////////////////
    class Block : public Statement
    {
      string             name_;
      int                type_;
      vector<Statement*> list_;
      map<string,Net*>   net_;
    public:
      enum
      {
	SEQUENTIAL,
	PARALLEL
      };
      Block(int type,const vector<Statement*>& list):
	type_(type),
	list_(list)
      {}
      Block(int type,const vector<Statement*>& list,
	    const char* name,const map<string,Net*>& net):
	type_(type),
	list_(list),
	name_(name),
	net_(net)
      {}
      Block(int type):
	type_(type)
      {}
      Block(){}
      virtual ~Block();
      
      const vector<Statement*>& list() const { return list_; }
      const map<string,Net*>&   net()  const { return net_; }

      void  setNet(map<string,Net*>& net){ net_ =net; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;

      void chain(set<const Statement*>& ss) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Case : public Statement
    {
    public:
      ////////////////////////////////////////////////////////////////////////
      class Item : public Statement
      {
	vector<Expression*> expr_;
	Statement*          stat_;
      public:
	Item(vector<Expression*> expr,Statement* stat):
	  expr_(expr),
	  stat_(stat)
	{}
	Item(Statement* stat):
	  stat_(stat)
	{}
	Item():
	  stat_(NULL)
	{}
	virtual ~Item();

	const vector<Expression*>& expression() const { return expr_; }
	const Statement* statement() const { return stat_; }

	void toXML(std::ostream& ostr,int indent=0) const;
	void toVerilog(std::ostream& ostr,int indent=0) const;

	void link(const map<string,Net*>& net,Module* mod);
	Item* clone(const string& hname) const;

	void chain(set<const Statement*>& ss) const;

	void callback(Callback& cb) const;
      };
    private:
      int           type_;
      Expression*   expr_;
      vector<Item*> items_;
    public:
      enum
      {
	CASE,
	CASEX,
	CASEZ
      };

      Case(int type,Expression* ex,const vector<Item*>& it):
	type_(type),
	expr_(ex),
	items_(it)
      {}
      Case():
	expr_(NULL)
      {}
      virtual ~Case();
      int type() const { return type_; }
      Expression* expression() const { return expr_; }
      const vector<Item*>& items() const { return items_; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;

      void chain(set<const Statement*>& ss) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Condition : public Statement
    {
      Expression* expr_;
      Statement*  true_;
      Statement*  false_;
    public:
      Condition(Expression* ex,Statement* t,Statement* f=NULL):
	expr_(ex),
	true_(t),
	false_(f)
      {}
      Condition():
	expr_(NULL),
	true_(NULL),
	false_(NULL)
      {}
      virtual ~Condition();
      const Expression* expression() const { return expr_; }
      const Statement*  trueStatement() const { return true_; }
      const Statement*  falseStatement() const { return false_; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;

      void chain(set<const Statement*>& ss) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class EventStatement : public Statement
    {
      vector<Event*> event_;
      Statement*     stat_;
    public:
      EventStatement(const vector<Event*>& ee):
	event_(ee),
	stat_(NULL)
      {}
      EventStatement(Event*ee):
	event_(1),
	stat_(NULL)
      {
	event_[0] = ee;
      }
      EventStatement():
	stat_(NULL)
      {}
      virtual ~EventStatement();
      const vector<Event*>& event() const { return event_; }
      const Statement* statement() const { return stat_; }
      void setStatement(Statement* stat){ stat_ =stat; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;

      void chain(set<const Statement*>& ss) const;

      bool isEdge() const;
      bool isLevel() const;
      bool isStorage() const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Assign : public Statement
    {
      int         type_;
      Expression* lval_;
      Expression* rval_;
    public:
      enum
      {
	BLOCKING,
	NONBLOCKING
      };
      Assign(int type,Expression* lval,Expression* rval):
	type_(type),
	lval_(lval),
	rval_(rval)
      {}
      Assign():
	lval_(NULL),
	rval_(NULL)
      {}
      virtual ~Assign();
      int type() const { return type_; }
      const Expression* leftValue()  const { return lval_; }
      const Expression* rightValue() const { return rval_; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;
      bool isSimple() const;
      bool isSimpleLeft() const;
      bool isSimpleRight() const;

      void chain(set<const Statement*>& ss) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class For : public Statement
    {
      Identifier* ita_;
      Expression* begin_;
      Expression* cond_;
      Expression* reach_;
      Statement*  stat_;
    public:
      For(Identifier* i1,Expression* e1,
	  Expression* e2,
	  Identifier* i2,Expression* e3,
	  Statement* s);
      For():
	ita_(NULL),
	begin_(NULL),
	cond_(NULL),
	reach_(NULL),
	stat_(NULL)
      {}
      virtual ~For();
      const Identifier* iterat() const { return ita_; }
      const Expression* begin() const { return begin_; }
      const Expression* condition() const { return cond_; }
      const Expression* reach() const { return reach_; }
      const Statement*  statement() const { return stat_; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(const map<string,Net*>& net,Module* mod);
      Statement* clone(const string& hname) const;

      void chain(set<const Statement*>& ss) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Function
    {
      vector<string>   port_;
      map<string,Net*> net_;
      Statement*       stat_;
    public:
      Function():
	stat_(NULL)
      {}
      virtual ~Function();
      const vector<string>&   port()      const { return port_; }
      const map<string,Net*>& net()       const { return net_; }
      const Statement*        statement() const { return stat_; }

      void addNet(const char* name,Net* net);
      void setStatement(Statement* stat) { stat_=stat; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(Module* mod);
      Function* clone(const string& hname) const;

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////
    class Process
    {
      int        type_;
      Statement* stat_;
      string     name_;

      set<const Net*> eventChain_;
      set<const Net*> leftChain_;
      set<const Net*> rightChain_;

      set<const Net*> nbLeftChain_;
      set<const Net*> nbRightChain_;

      set<const Net*> bLeftChain_;
      set<const Net*> bRightChain_;

      set<const Statement*> statChain_;
    public:
      enum
      {
	INITIAL,
	TASK,
	ALWAYS,
	ASSIGN,
	PARAMETER
      };
      Process(int type,Statement* stat=NULL):
	type_(type),
	stat_(stat)
      {}
      Process():
	stat_(NULL)
      {}
      virtual ~Process();
      int type() const { return type_; }
      const Statement* statement() const { return stat_; }

      void toXML(std::ostream& ostr,int indent=0) const;
      void toVerilog(std::ostream& ostr,int indent=0) const;

      void link(Module* mod);
      Process* clone(const string& hname) const;

      bool isEdge() const;
      bool isLevel() const;
      bool isStorage() const;
      const Statement* queryStatement(int type,const Net* src) const;

      const set<const Net*>& eventChain() const { return eventChain_; }
      const set<const Net*>& leftChain()  const { return leftChain_; }
      const set<const Net*>& rightChain() const { return rightChain_; }

      const set<const Net*>& nbLeftChain()  const { return nbLeftChain_; }
      const set<const Net*>& nbRightChain() const { return nbRightChain_; }
      const set<const Net*>& bLeftChain()  const { return bLeftChain_; }
      const set<const Net*>& bRightChain() const { return bRightChain_; }

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////    
    class Gate
    {
    public:
      enum
      {
	AND,
	NAND,
	OR,
	NOR,
	XOR,
	XNOR,
	BUF,
	BUFIF0,
	BUFIF1,
	NOT,
	NOTIF0,
	NOTIF1,
	PULLDOWN,
	PULLUP,
	NMOS,
	RNMOS,
	PMOS,
	RPMOS,
	CMOS,
	RCMOS,
	TRAN,
	RTRAN, 
	TRANIF0,
	TRANIF1,
	RTRANIF0,
	RTRANIF1
      };

      int                 type_;
      vector<Expression*> pin_;
    public:
      Gate(int t,const vector<Expression*>& pin):
	type_(t),
	pin_(pin)
      {}
      Gate(){}
      virtual ~Gate();

      void callback(Callback& cb) const;
    };
    ////////////////////////////////////////////////////////////////////////    
    class Instance
    {
      ////////////////////////////////////////////////////////////////////////    
    public:
      class Port
      {
	string      ref_;
	Expression* con_;
	Net*        net_;
      public: