verilog2c++.cc

将Verilog代码转换成C++代码的软件

	    for( ii=func->port().begin();ii!=func->port().end();++ii )
	      {
		Net* net =func->net().find(*ii)->second;
		if( net->type()==Net::FUNCTION )
		  {
		    hhstr << setw(indent) << "";
		    printClass(hhstr,net->width());
		    //		    hhstr.form("f%08X",net);
		    hhstr << 'f' << (uint)net;
		    
		    hhstr << '(';
		  }
	      }
	    for( ii=func->port().begin();ii!=func->port().end();++ii )
	      {
		Net* net =func->net().find(*ii)->second;
		if( net->interface()==Net::INPUT )
		  {
		    if( second )
		      hhstr << ',';
		    
		    printRef(hhstr,net->width());
		    hhstr << ' ';
		    //		    hhstr.form("n%08X",net);
		    hhstr << 'n' << (uint)net;
		    
		    second=true;
		  }
	      }
	    hhstr << ");" << endl;
	  }
      }

    
      ////////////////////////////////////
      hhstr << setw(indent-2) << "" << "public:" << endl;
      hhstr << setw(indent) << "" << findName( top_ ) << "(){}" << endl;
      hhstr << setw(indent) << "" << '~' << findName( top_ ) << "(){}" << endl;
      
      

      ////////////////////////////////////
      // vcd
      if( vcd )
	{
	  hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";
	  hhstr << setw(indent) << "" << "void vcd_open(std::ostream& str);\n";
	  hhstr << setw(indent) << "" << "void vcd_close();\n";
	}

      
      ////////////////////////////////////
      // port
      {
	hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";
	map<string,Net*>::const_iterator i;
	for( i=top_->net().begin();i!=top_->net().end();++i )
	  {
	    if( syncsrc_.find( i->second )==syncsrc_.end() )
	      if( (i->second->interface()!=Net::PRIVATE) )
		{
		  printPort(hhstr,indent,i->second,i->first);
		  /*
		  printPort(hhstr,i->second->width(),indent);
		  hhstr << i->first << "() { return ";
		  //		  hhstr.form("n%08X",i->second);
		  hhstr << 'n' << (uint)i->second;
		  hhstr << "; }\n";
		  */
		  hhstr << "\n";

		  vcdNet.insert( i->second );
		}
	  }
      }
      
  
      ////////////////////////////////////
      // temporal event signals
      {
	vector<Synchronous>::const_iterator i;
	for( i=sync_.begin();i!=sync_.end();++i )
	  {
	    hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";
	    
	    hhstr << setw(indent) << "" << "void ";
	    hhstr << top_->findName( (*i).net() );
	    
	    if( (*i).type()==Event::POSEDGE )
	      hhstr << "_posedge";
	    else if( (*i).type()==Event::NEGEDGE )
	      hhstr << "_negedge";
	    else
	      hhstr << "_anyedge";	    
	    
	    hhstr << "();" << endl;
	  }
      }
      
      
      indent-=2;hhstr << setw(--indent) << "" << "};" << endl;
      indent-=2;hhstr << setw(indent) << "" << '}' << endl;
      
      
      
      ////////////////////////////////////////////////////////////////////////
      ////////////////////////////////////////////////////////////////////////
      ////////////////////////////////////////////////////////////////////////
      
      fname =string(path) + findName( top_ ) + ".cc";
      std::ofstream ccstr(fname.c_str());
      indent=0;
      
      
      ////////////////////////////////////////////////////////
      // create contents file
      {
	ccstr << setw(indent) << "" << "#include \"" << findName( top_ ) <<  ".hh\"" << endl;
	
	ccstr << setw(indent) << "" << "namespace moe" << endl;
	ccstr << setw(indent) << "" << '{' << endl;
	indent+=2;
      }
      

      ////////////////////////////////////
      // function
      {
	ccstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";
	
        map<string,Function*>::const_iterator i;
        for( i=top_->function().begin();i!=top_->function().end();++i )
          {
	    Function* func =i->second;
	    vector<string>::const_iterator ii;
	    bool second=false;
	    for( ii=func->port().begin();ii!=func->port().end();++ii )
	      {
		Net* net =func->net().find(*ii)->second;
		if( net->type()==Net::FUNCTION )
		  {
		    ccstr << setw(indent) << "";
		    printClass(ccstr,net->width());
		    ccstr << findName( top_ ) << "::";
		    //		    ccstr.form("f%08X",net);
		    ccstr << 'f' << (uint)net;
		    ccstr << '(';
		  }
	      }
	    for( ii=func->port().begin();ii!=func->port().end();++ii )
	      {
		Net* net =func->net().find(*ii)->second;
		if( net->interface()==Net::INPUT )
		  {
		    if( second )
		      ccstr << ',';
		    
		    printRef(ccstr,net->width());
		    ccstr << ' ';
		    
		    //		    ccstr.form("n%08X",net);
		    ccstr << 'n' << (uint)net;
		    
		    second=true;
		  }
	      }
	    ccstr << ')' << endl;
	    ccstr << setw(indent) << "" << '{' << endl;indent+=2;
	    

	    for( ii=func->port().begin();ii!=func->port().end();++ii )
	      {
		Net* net =func->net().find(*ii)->second;
		
		if( net->interface()==Net::PRIVATE )
		  if( net->type()==Net::REG )
		      {
			ccstr << setw(indent) << "";
			printRef(ccstr,net->width());
			ccstr << ' ';
			//		    ccstr.form("n%08X",net);
			ccstr << 'n' << (uint)net;
			ccstr << ";\n";
		      }
	      }

	    {
	      StatementSplice cpp(comm,ccstr,flipflop_,indent);
	      {
		if( comm )
		  {
		    ccstr << setw(indent) << "" << '/' << "************************************" << endl;
		    i->second->statement()->toVerilog(ccstr,indent+2);
		    ccstr << setw(indent) << "" << '*' << '/' << endl;
		  }

		i->second->statement()->callback( cpp );
	      }
	    }

	    indent-=2;ccstr << setw(indent) << "" << '}' << endl;


	  }
      }


      /***
      ////////////////////////////////////
      // do anything signals
      {
	ccstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";

	ccstr << setw(indent) << "" << "void ";
	ccstr << findName( top_ ) << "::" << "_anything()\n";

	ccstr << setw(indent) << "" << '{' << endl;indent+=2;
	{
	  StatementSplice cpp(comm,ccstr,flipflop_,indent);
	  list<Handle>::const_iterator ii;
	  for( ii=anysync_.handle().begin();ii!=anysync_.handle().end();++ii )
	    if( (*ii).statement()!=NULL )
	      {
		if( comm )
		  {
		    ccstr << setw(indent) << "" << '/' << "************************************" << endl;
		    (*ii).statement()->toVerilog(ccstr,indent+2);
		    ccstr << setw(indent) << "" << '*' << '/' << endl;
		  }
		
		(*ii).statement()->callback( cpp );
	      }
	}
	indent-=2;ccstr << setw(indent) << "" << '}' << endl;
      }
      ***/



      ////////////////////////////////////
      // temporal event signals
      {
	vector<Synchronous>::const_iterator i;
	for( i=sync_.begin();i!=sync_.end();++i )
	  {
	    ccstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";

	    ccstr << setw(indent) << "" << "void ";
	    ccstr << findName( top_ ) << "::";
	    ccstr << top_->findName( (*i).net() );

	    if( (*i).type()==Event::POSEDGE )
	      ccstr << "_posedge";
	    else if( (*i).type()==Event::NEGEDGE )
	      ccstr << "_negedge";
	    else
	      ccstr << "_anyedge";	    

	    ccstr << "()" << endl;

	    ////////////////////////////////////
	    ccstr << setw(indent) << "" << '{' << endl;indent+=2;
	    {
	      map<string,Net*>::const_iterator i;
	      for( i=top_->net().begin();i!=top_->net().end();++i )
		{
		  if( flipflop_.find(i->second)==flipflop_.end() )
		    {
		      if( (i->second->interface()==Net::PRIVATE) )
			{
			  ccstr << setw(indent) << "";
			  printClass(ccstr,i->second->width());
			  //			  ccstr.form("n%08X;",i->second);
			  ccstr << 'n' << (uint)i->second << ';';
			  if( comm )
			    ccstr << " // " << i->first << ":private";
			  ccstr << endl;

			  vcdNet.insert( i->second );
			}
		    }
		  else
		    {
		      if( i->second->isArray() )
			{
			  ccstr << setw(indent) << "";
			  printClass(ccstr,i->second->width());
			  //			  ccstr.form("d%08X;",i->second);
			  ccstr << 'd' << (uint)i->second << ';';
			  if( comm )
			    ccstr << " // " << i->first << ":data";
			  ccstr << endl;

			  ccstr << setw(indent) << "" << "uint32_t   ";
			  //			  ccstr.form("a%08X;",i->second);
			  ccstr << 'a' << (uint)i->second << ';';
			  if( comm )
			    ccstr << " // " << i->first << ":address";
			  ccstr << endl;
			  
			  ccstr << setw(indent) << "" << "bool       ";
			  //			  ccstr.form("u%08X",i->second);
			  ccstr << 'u' << (uint)i->second;
			  ccstr << " =false;";
			  if( comm )
			    ccstr << " // " << i->first << ":update";
			  ccstr << endl;
			}
		      else
			{
			  ccstr << setw(indent) << "";
			  printClass(ccstr,i->second->width());
			  //			  ccstr.form("d%08X =n%08X;",i->second,i->second);
			  ccstr << 'd' << (uint)i->second << " =n" << (uint)i->second << ';';
			  if( comm )
			    ccstr << " // " << i->first << ":data";
			  ccstr << endl;

			  ccstr << setw(indent) << "" << "bool       ";
			  //			  ccstr.form("u%08X",i->second);
			  ccstr << 'u' << (uint)i->second;
			  ccstr << " =false;";
			  if( comm )
			    ccstr << " // " << i->first << ":update";
			  ccstr << endl;
			}
		    }
		}
	    }
	    ////////////////////////////////////
	    {
	      StatementSplice cpp(comm,ccstr,flipflop_,indent);
	      list<Handle>::const_iterator ii;
	      for( ii=(*i).handle().begin();ii!=(*i).handle().end();++ii )
		if( (*ii).statement()!=NULL )
		  {
		    if( comm )
		      {
			ccstr << setw(indent) << "" << '/' << "************************************" << endl;
			
			(*ii).statement()->toVerilog(ccstr,indent+2);
			ccstr << setw(indent) << "" << '*' << '/' << endl;
		      }

		    (*ii).statement()->callback( cpp );
		  }
	    }
	    ////////////////////////////////////
	    {
	      map<string,Net*>::const_iterator i;
	      for( i=top_->net().begin();i!=top_->net().end();++i )
		{
		  if( flipflop_.find(i->second)!=flipflop_.end() )
		    {
		      if( i->second->isArray() )
			{
			  ccstr << setw(indent) << "";
			  //			  ccstr.form("if( u%08X )\n",i->second);
			  ccstr << "if( u" << (uint)i->second << " )\n";
			  indent+=2;
		      
			  ccstr << setw(indent) << "";
			  //			  ccstr.form("n%08X[a%08X] =d%08X;\n",i->second,i->second,i->second);
			  ccstr << 'n' << (uint)i->second << "[a" << (uint)i->second << "] =d" << (uint)i->second << ";\n";
			  indent-=2;
			}
		      else
			{
			  ccstr << setw(indent) << "";
			  //			  ccstr.form("n%08X =d%08X;\n",i->second,i->second);
			  ccstr << 'n' << (uint)i->second << " =d" << (uint)i->second << ";\n";
			}

		      ////////////////////////////////////
		      /**
			 ccstr << setw(indent) << "";
			 // ccstr.form("b%08X =u%08X;\n",i->second,i->second);
		      ccstr << 'b' << (uint)i->second << " =u" << (uint)i->second << ";\n";
		      **/
		    }
		}
	    }
	    ////////////////////////////////////
	    //	    ccstr << setw(indent) << "" << "_anything();\n";

	    {
	      StatementSplice cpp(comm,ccstr,flipflop_,indent);
	      list<Handle>::const_iterator ii;
	      for( ii=anysync_.handle().begin();ii!=anysync_.handle().end();++ii )
		if( (*ii).statement()!=NULL )
		  {
		    if( comm )
		      {
			ccstr << setw(indent) << "" << '/' << "************************************" << endl;
			(*ii).statement()->toVerilog(ccstr,indent+2);
			ccstr << setw(indent) << "" << '*' << '/' << endl;
		      }
		    
		    (*ii).statement()->callback( cpp );
		  }
	    }

	    

	    ////////////////////////////////////
	    // vcd
	    if( vcd )
	    {
	      ccstr << setw(indent) << "" << "*vcd_ << \'#\' << time_ << \'\\n\';\n";
	      
	      const char* cptr;
	      set<const Net*>::const_iterator i;
	      for( i=vcdNet.begin();i!=vcdNet.end();++i )
		if( !((*i)->isArray()) )
		  {
		    ccstr << setw(indent) << "" << "vcd_dump(*vcd_,";
		    //		    ccstr.form("n%08X",(*i));
		    ccstr << 'n' << (uint)(*i);
		    ccstr << ',';
		    ccstr << (*i)->width() << ");";
		    ccstr << "*vcd_ << \" ";
		    //		    ccstr.form("n%08X",(*i));
		    ccstr << 'n' << (uint)(*i);
		    ccstr << "\\n\";\n";
		  }
	      ccstr << setw(indent) << "" << "time_ +=1;\n";
	    }



	    ////////////////////////////////////
	    indent-=2;ccstr << setw(indent) << "" << '}' << endl;
	  }
      }



      ////////////////////////////////////
      // vcd support
      if( vcd )
	{
	  ccstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n";
	  
	  
	  ccstr << setw(indent) << "" << "void ";
	  ccstr << findName( top_ ) << "::";
	  ccstr << "vcd_open(std::ostream& str)\n";
	  ccstr << setw(indent) << "" << '{' << endl;indent+=2;
	  {
	    ccstr << setw(indent) << "" << "vcd_ =&str;\n";
	    ccstr << setw(indent) << "" << "time_ =0;\n";
	    
	    ccstr << setw(indent) << "" << "*vcd_ << \"$version\\n\";\n";
	    ccstr << setw(indent) << "" << "*vcd_ << \" moe verilog simulation\\n\";\n";
	    ccstr << setw(indent) << "" << "*vcd_ << \"$end\\n\";\n";
	    
	    {
	      const char* cptr;
	      set<const Net*>::const_iterator i;
	      for( i=vcdNet.begin();i!=vcdNet.end();++i )
		if( !((*i)->isArray()) )
		  {
		    ccstr << setw(indent) << "" << "*vcd_ << \"$var reg ";
		    ccstr << (*i)->width() << ' ';
		    //		    ccstr.form("n%08X",(*i));
		    ccstr << 'n' << (uint)(*i);
		    ccstr << ' ';
		    cptr =top_->findName( *i );
		    if( *cptr=='\\' )
		      cptr++;
		    ccstr << ' ' << cptr;
		    if( (*i)->width() > 1 )
		      {
			ccstr << " [ ";
			ccstr << (*i)->msb()->calcConstant();
			ccstr << " : ";
			ccstr << (*i)->lsb()->calcConstant();
			ccstr << " ]";
		      }
		    ccstr << " $end\\n\";\n";
		  }
	    }
	    ccstr << setw(indent) << "" << "*vcd_ << \"$enddefinitions $end\\n\";\n";
	    ccstr << setw(indent) << "" << "*vcd_ << \"$dumpvars\\n\";\n";
	  }

	  indent-=2;ccstr << setw(indent) << "" << '}' << endl;
	  
	  
	  ccstr << setw(indent) << "" << "void ";
	  ccstr << findName( top_ ) << "::";
	  ccstr << "vcd_close()\n";
	  ccstr << setw(indent) << "" << '{' << endl;indent+=2;
	  {
	    ccstr << setw(indent) << "" << "*vcd_ << \"$end\\n\";\n";
	    ccstr << setw(indent) << "" << "vcd_->flush();\n";
	  }
	  indent-=2;ccstr << setw(indent) << "" << '}' << endl;
	}


      ////////////////////////////////////
      indent-=2;ccstr << setw(indent) << "" << '}' << endl;
    }
    ////////////////////////////////////////////////////////////////////////
  };
  
}


////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////

int main(int argc,char* argv[])
{
  if( argc==1 )
    {
      //      cout << "Verilog2C++ file-name.(v|v2k) module-name ( (posedge|negedge) port-name )+ comments? dumpvars? debug? \n";
      cout << "Verilog2C++ file-name.(v|v2k) module-name ( (posedge|negedge) port-name )+ comments?\n";
      exit(1);
    }
  bool comments =false;
  bool dumpvars =false;
  bool debug    =false;
  int i;
  for( i=3;i<argc;i++ )
    {
      if( strcmp(argv[i],"comments" )==0 )
	comments=true;
      else if( strcmp(argv[i],"dumpvars" )==0 )
	dumpvars=true;
      else if( strcmp(argv[i],"debug" )==0 )
	debug=true;
    }

  moe::Convert conv(debug);
  
  cerr << "load...\n";
  conv.parse( argv[1] );

  cerr << "link module...\n";
  conv.link();

  conv.setTop( argv[2] );

  for( i=3;i<argc;i+=2 )
    {
      if( strcmp(argv[i],"posedge" )==0 )
	conv.setSynchronous( argv[i+1],moe::Verilog::Event::POSEDGE);
      else if( strcmp(argv[i],"negedge" )==0 )
	conv.setSynchronous( argv[i+1],moe::Verilog::Event::NEGEDGE);
    }

  conv.setAnything();

  conv.toEmVer("./",comments,dumpvars);
}