📄 verilog2c++.cc
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printProgress(std::cerr,(100.0*curr)/total); vector<Process*>::const_iterator i; for( i=top_->process().begin();i!=top_->process().end();++i ) { curr ++; if( typeid( *((*i)->statement()) )==typeid( Assign ) ) { Assign* ass=(Assign*)(*i)->statement(); if( ass->isSimple() ) if( typeid( *(ass->rightValue()) )==typeid( Identifier )&& ((Identifier*)ass->rightValue())->net()==net ) _trace(((Identifier*)ass->leftValue())->net(),type,sync,curr,total); } else { const Statement* stat; stat =(*i)->queryStatement(type,net); if( stat!=NULL ) { set<const Net*> right; RightNetChainCB cb( right ); stat->callback( cb ); Handle handle(stat); handle.setRight( right ); sync.handle().push_back( handle ); } } } } bool trace(const Net* net,int type,Synchronous& sync) { printProgress(std::cerr,-1); int curr=0; int total=0; vector<Process*>::const_iterator i; for( i=top_->process().begin();i!=top_->process().end();++i ) { curr ++; if( typeid( *((*i)->statement()) )==typeid( Assign ) ) { Assign* ass=(Assign*)(*i)->statement(); if( ass->isSimple() ) if( typeid( *(ass->rightValue()) )==typeid( Identifier )&& ((Identifier*)ass->rightValue())->net()==net ) _trace(((Identifier*)ass->leftValue())->net(),type,sync,curr,total); } else { const Statement* stat; stat =(*i)->queryStatement(type,net); if( stat!=NULL ) { set<const Net*> right; RightNetChainCB cb( right ); stat->callback( cb ); Handle handle(stat); handle.setRight( right ); sync.handle().push_back( handle ); } } } printProgress(std::cerr,100.0); return true; } //////////////////////////////////////////////////////////////////////// void _relate(const Net* net, set<const Net*>& actnet, set<const Statement*>& actstat, list<Handle>& chain) { if( actnet.find(net)==actnet.end() ) { actnet.insert( net ); multimap<const Net*,const Statement*>::const_iterator i; set<const Net*>::const_iterator ii; i =map_.find( net ); if( i!=map_.end() ) { do { if( actstat.find( i->second )==actstat.end() ) { actstat.insert( i->second ); set<const Net*> left; set<const Net*> right; LeftNetChainCB lcb( left ); RightNetChainCB rcb( right ); i->second->callback( lcb ); i->second->callback( rcb ); Handle handle( i->second ); handle.setRight( right ); handle.setLeft( left ); chain.push_front( handle ); for( ii=right.begin();ii!=right.end();++ii ) _relate(*ii,actnet,actstat,chain); } i++; } while( i!=map_.upper_bound( net ) ); } } } //////////////////////////////////// bool relate(list<Handle>& chain) { set<const Net*> actnet; set<const Statement*> actstat; list<Handle>::const_iterator i; set<const Net*>::const_iterator ii; double per =0.0; double step =100.0/chain.size(); printProgress(std::cerr,-1); for( i=chain.begin();i!=chain.end();++i ) { printProgress(std::cerr,per); per +=step; for( ii=(*i).right().begin();ii!=(*i).right().end();++ii ) _relate(*ii,actnet,actstat,chain); } printProgress(std::cerr,100.0); return true; } //////////////////////////////////////////////////////////////////////// bool _inclusion(const set<const Net*>& l,const set<const Net*>& r) { set<const Net*>::const_iterator i; for( i=l.begin();i!=l.end();++i ) if( r.find( *i )!=r.end() ) return true; return false; } //////////////////////////////////// bool inspect(list<Handle>& chain) { list<Handle>::iterator i; list<Handle>::iterator ii; double per =0.0; double step =100.0/chain.size(); printProgress(std::cerr,-1); for( i=chain.begin();i!=chain.end();++i ) { printProgress(std::cerr,per); per +=step; for( ii=i;ii!=chain.end();++ii ) { if( i!=ii ) if( _inclusion( (*i).right(),(*ii).left() ) ) { chain.insert( i,(*ii) ); chain.erase( ii ); return true; } } } printProgress(std::cerr,100.0); return false; } //////////////////////////////////// bool sort(list<Handle>& chain) { bool swap; set<const Handle*> loop; list<Handle>::iterator i; list<Handle>::iterator ii; double per =0.0; double step =100.0/chain.size(); printProgress(std::cerr,-1); for( i=chain.begin();i!=chain.end();++i ) { printProgress(std::cerr,per); per +=step; do { for( ii=i;ii!=chain.end();++ii ) { swap=false; if( i!=ii ) if( _inclusion( (*i).right(),(*ii).left() ) ) { if( loop.find( &(*ii) )!=loop.end() ) { std::cerr << "\nlacing error !\n"; (*ii).statement()->toVerilog(cerr,0); return false; } i =chain.insert( i,(*ii) ); chain.erase( ii ); loop.insert( &(*ii) ); swap=true; break; } if( swap ) break; } } while( swap ); loop.clear(); } printProgress(std::cerr,100.0); return true; } //////////////////////////////////////////////////////////////////////// public: Convert(bool debug=false): Verilog(debug), top_(NULL), anysync_(NULL,Event::ANYEDGE) {} ~Convert(){} const vector<Synchronous>& synchronous() const { return sync_; } const set<const Net*>& latch() const { return latch_; } const set<const Net*>& flipflop() const { return flipflop_; } // const set<const Net*>& constant() const { return constant_; } // const set<const Net*>& input() const { return input_; } // const set<const Net*>& output() const { return output_; } const multimap<const Net*,const Statement*>& handle() const { return map_; } //////////////////////////////////////////////////////////////////////// bool setTop(const char* name) { top_=findModule(name); if( top_!=NULL ) { cerr << "ungroup instance...\n"; top_->ungroup(); cerr << "link net...\n"; top_->link(); { vector<Process*>::const_iterator i; for( i=top_->process().begin();i!=top_->process().end();++i ) { if( (*i)->isStorage()&&(*i)->isEdge() ) { set<const Net*>::const_iterator ii; //for( ii=(*i)->leftChain().begin();ii!=(*i)->leftChain().end();++ii ) for( ii=(*i)->nbLeftChain().begin();ii!=(*i)->nbLeftChain().end();++ii ) { flipflop_.insert( (*ii) ); } } else { if( (*i)->isStorage()&&(*i)->isLevel() ) latch_.insert( (*i)->leftChain().begin(),(*i)->leftChain().end() ); switch( (*i)->type() ) { case Process::ASSIGN: { set<const Net*>::const_iterator ii; for( ii=(*i)->leftChain().begin();ii!=(*i)->leftChain().end();++ii ) map_.insert( pair<const Net*,const Statement*> ((*ii),(*i)->statement()) ); } break; case Process::ALWAYS: { if( typeid( *(*i)->statement() )==typeid( EventStatement ) ) { if( typeid( *( ((EventStatement*)(*i)->statement())->statement() ) )== typeid( Block ) ) { /** vector<Statement*>::const_iterator ii; for( ii=((Block*)(((EventStatement*)(*i)->statement())->statement()))->list().begin(); ii!=((Block*)(((EventStatement*)(*i)->statement())->statement()))->list().end(); ++ii ) { set<const Net*> chain; LeftNetChainCB cb(chain); (*ii)->callback(cb); set<const Net*>::const_iterator iii; for( iii=chain.begin();iii!=chain.end();++iii ) map_.insert( pair<const Net*,const Statement*> ((*iii),(*ii)) ); } **/ set<const Net*>::const_iterator ii; for( ii=(*i)->leftChain().begin();ii!=(*i)->leftChain().end();++ii ) map_.insert( pair<const Net*,const Statement*> ((*ii), ((EventStatement*)(*i)->statement())->statement()) ); } else { set<const Net*>::const_iterator ii; for( ii=(*i)->leftChain().begin();ii!=(*i)->leftChain().end();++ii ) map_.insert( pair<const Net*,const Statement*> ((*ii), ((EventStatement*)(*i)->statement())->statement()) ); } } } break; } } } } return true; } else return false; } //////////////////////////////////////////////////////////////////////// bool setSynchronous(const char* name,int type) { if( top_!=NULL ) { bool ret; const Net* net =top_->findNet(name); if( net!=NULL ) { syncsrc_.insert(net); std::cerr << "synchronous source : "; std::cerr << name; if( type==Event::POSEDGE ) std::cerr << ".posedge"; else if( type==Event::NEGEDGE ) std::cerr << ".negedge"; else std::cerr << ".anyedge"; std::cerr << endl; sync_.push_back( Synchronous(net,type) ); std::cerr << "trace... "; trace(net,type,sync_.back()); std::cerr << '\n'; std::cerr << "relate... "; ret =relate(sync_.back().handle()); std::cerr << '\n'; std::cerr << "sort... "; sort(sync_.back().handle()); std::cerr << '\n'; std::cerr << "inspect... "; inspect(sync_.back().handle()); std::cerr << '\n'; return ret; } } return false; } bool setAnything() { if( top_!=NULL ) { bool ret; std::cerr << "anything source... \n"; { map<string,Net*>::const_iterator i; for( i=top_->net().begin();i!=top_->net().end();++i ) { if( ((i->second->interface()==Net::OUTPUT)|| (i->second->interface()==Net::INOUT))&& (flipflop_.find(i->second)==flipflop_.end()) ) { set<const Net*> right; right.insert( i->second ); Handle handle(NULL); handle.setRight( right ); anysync_.handle().push_back( handle ); } } } std::cerr << "relate... "; ret =relate(anysync_.handle()); std::cerr << '\n'; std::cerr << "sort... "; sort(anysync_.handle()); std::cerr << '\n'; std::cerr << "inspect... "; inspect(anysync_.handle()); std::cerr << '\n'; return ret; } else return false; } //////////////////////////////////////////////////////////////////////// void toEmVer(const char* path,bool comm=false,bool vcd=false) { string fname; int indent; set<const Net*> vcdNet; //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////// fname =string(path) + findName( top_ ) + ".hh"; std::ofstream hhstr(fname.c_str()); indent=0; //////////////////////////////////////////////////////// // create header file hhstr << setw(indent) << "" << "#include <EmVer.hh>" << endl; hhstr << setw(indent) << "" << "namespace moe" << endl; hhstr << setw(indent) << "" << '{' << endl; indent+=2; hhstr << setw(indent) << "" << "class " << findName( top_ ) << ": public EmVer" << endl; hhstr << setw(indent) << "" << "{" << endl;indent+=2; //////////////////////////////////// // vcd if( vcd ) { hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n"; hhstr << setw(indent) << "" << "std::ostream* vcd_;\n"; hhstr << setw(indent) << "" << "long time_;\n"; hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n"; } /*** //////////////////////////////////// // constant { set<string>::const_iterator i; for( i=pool(Number()).begin();i!=pool(Number()).end();++i ) { if( (*i).size()>64 ) { hhstr << setw(indent) << "" << "UIntN<" << setw(3) << (*i).size() << "> "; hhstr.form("c%08X;",i); if( comm ) hhstr << " // " << (*i) << ".constant"; hhstr << endl; } } } ***/ //////////////////////////////////// // regist { map<string,Net*>::const_iterator i; for( i=top_->net().begin();i!=top_->net().end();++i ) { if( syncsrc_.find( i->second )==syncsrc_.end() ) { if( (i->second->interface()!=Net::PRIVATE)|| (flipflop_.find(i->second)!=flipflop_.end())|| (latch_.find(i->second)!=latch_.end()) ) { printNet(hhstr,indent,i->second); /** printClass(hhstr,i->second->width(),indent); // hhstr.form("n%08X",i->second); hhstr << 'n' << (uint)i->second; if( i->second->isArray() ) hhstr << '[' << i->second->depth() << ']'; hhstr << ";"; **/ if( comm ) { hhstr << " // " << i->first; if( flipflop_.find(i->second)!=flipflop_.end() ) hhstr << ":flipflop"; if( latch_.find(i->second)!=latch_.end() ) hhstr << ":latch"; if( i->second->interface()!=Net::PRIVATE ) hhstr << ":port"; } hhstr << endl; vcdNet.insert( i->second ); //////////////////////////////////// /** if( flipflop_.find(i->second)!=flipflop_.end() ) { hhstr << setw(indent) << "" << "bool "; // hhstr.form("b%08X",i->second); hhstr << 'b' << (uint)i->second; hhstr << ";"; if( comm ) { hhstr << " // " << i->first; if( flipflop_.find(i->second)!=flipflop_.end() ) hhstr << ":booth"; } hhstr << endl; } **/ } } } } //////////////////////////////////// // function { hhstr << setw(indent) << "" << "////////////////////////////////////////////////////////////////////////\n"; map<string,Function*>::const_iterator i; for( i=top_->function().begin();i!=top_->function().end();++i ) { Function* func =i->second; vector<string>::const_iterator ii; bool second=false;
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