elm - pci pio board.mht

不足20元的PCI设计

<P>Start of read cycle. DEVSEL# and TRDY# is deasserted. Normaly, =
DEVSEL# and=20
TRDY# are released at the next clock, and transits in the idol state =
(STATE 0).=20
But, it transits directly in STATE 2 or STATE 5 without passing through =
the idol=20
state when it faced this device under this state and I/O read/write =
command was=20
issued again. (fast back to back transaction)</P>
<H4>STATE 6</H4>
<P>Read cycle is in progress. Terget device asserts DEVSEL# and respond =
to the=20
read cycle. At the same time, output read data to the AD bus and assert =
TRDY#.=20
At this time, it transits to STATE 7 when IRDY# is being asserted =
(initiater can=20
accept read data) and FRAME# is being deasserted (last data).</P>
<H4>STATE 7</H4>
<P>Read cycle is finished. Terget device deasserts DEVSEL# and TRDY#. =
Then,=20
release DEVSEL# and TRDY# at the next clock, and it transits to the idol =

state.</P>
<H4>STATE 1</H4>
<P>This state number is not defined. Even if it goes into this condition =
due to=20
any error, it transits to STATE 0 at the next clock, and reverts to the=20
normality loop.</P></DIV>
<DIV class=3Dpara>
<H3>The Design Rule Violation</H3>
<P>Well, the circuit diagram is simplified in this experiment by partly =
omitting=20
the function required as a PCI device. I explain about the omitted =
function, and=20
the evil by that. It will specially never cause a trouble as an =
experiment made=20
with a PC though they are the contents which faint when the designer of =
the=20
normal PCI device sees it.</P>
<H4>There is no configration register.</H4>
<P>The existence of the device is recognized by a system by mounting=20
configuration register. It realize to set up the function as a PCI =
device or to=20
move terget address to avoid conflict.</P>
<P>The terget address is being decoded fixedly in this board without =
mounting=20
configuration register. You must set up terget address so that the =
conflict of=20
the resource may not occur because the existence of the device isn't =
recognized=20
by a system. A PCI board with a DIP switch will be laughed :-)</P>
<H4>There is no funftion of parity generation and check</H4>
<P>A parity error surely occurs in read cycle because the check or drive =
parity=20
signal aren't done. Any operation, such as NMI, occurs when parity error =
is=20
detected when parity error respond bit of configuration register of =
Initiater=20
(Host-PCI bridge) is set. But, it doesn't have an influence with the =
operation=20
even if parity generator isn't mounted because that bit is usually 0 in =
the=20
PC.</P>
<H4>Upper 16 bits of address is not decoded</H4>
<P>Only lower 16bit is being decoded by this board though 32bit full =
decoding is=20
required with PCI with an I/O device as well. But, it is no problem =
because the=20
access to the I/O space above 64K bytes doesn't occur in the =
PC.</P></DIV>
<DIV class=3Dpara>
<H3>Building the PCI Board</H3>
<DIV class=3Drset><IMG height=3D240 alt=3DPCB=20
src=3D"http://elm-chan.org/works/pci/pci_board.jpeg" width=3D320><BR><A=20
href=3D"http://elm-chan.org/works/pci/pci_io.png">Circuit Diagram</A> | =
<A=20
href=3D"http://elm-chan.org/works/pci/pci_pio.zip">PLD source =
file</A></DIV>
<P>The proto-board for PCI is MCC-331(Sunhayato). It has a mount =
bracket, so=20
that it is easy to use.</P>
<P>PLD should use the speed grade of <EM>7ns or faster</EM>. Even 7ns =
doesn't=20
satisfy specs with the specs of the bus timing. But, because to obtain =
the PLD=20
faster than 5ns is difficult, it is used in consideration of the margin. =
(It=20
will no problem.)</P>
<P>Any other parts except will not need to select manufacturer because =
they are=20
the just ordinary. Inputs and outputs are 16bit for each because it =
lacked the=20
mounting space of the connector this time though they were the places =
where=20
32bit wanted it respectively.</P><IMG class=3Drset height=3D160 =
alt=3Dwire=20
src=3D"http://elm-chan.org/works/pci/pci_wire.jpeg" width=3D213>=20
<P>Because it is a digital circuit, I think that it never takes care of=20
building. Because there is many wires, <A=20
href=3D"http://elm-chan.org/docs/wire/wiring_e.html">UEW</A> is suitable =
for=20
wiring. Don't use any other wire because it will become like a mountain. =
That=20
you must be the most careful is not to mistake wiring. So it is easy to =
mistake=20
because a terminal number is discontinuous at voltage key of the edge =
connector.=20
I actually mistook some times, too. :-) Especially, a mistake of the =
power=20
supply pins can destroy main board. Moreover, you should reinforce a =
power=20
supply line fully because it operates at high speed of maximum =
33MHz.</P></DIV>
<DIV class=3Dpara>
<H3>Test and Result</H3>
<P>First, set the I/O address of this board with dip-switch. Because =
lower 2bit=20
isn't being decoded, 4bytes that it continued is decided to be occupied. =
A bus=20
will conflict when the I/O address duplicates with any other PCI devices =
at this=20
time. It is needless to say that you must choose the I/O address which =
no one is=20
using.</P>
<P>When for example F300h is set, this board responds to the access from =
F300h=20
to F303h,</P>
<P>Well, let's go with the performance check if you can confirm that it =
operates=20
completely. Performance test counts cycles per second that access terget =
device=20
with I/O string operating instructions. The result is as =
follows:</P><BR><IMG=20
height=3D260 alt=3DResult =
src=3D"http://elm-chan.org/works/pci/pci_speed.png"=20
width=3D550><BR><BR>
<P>Though it is natural, PCI showed an overwhelming speed in comparison =
with=20
ISA. As for the write operation, 6clks/cycle, a read operation become=20
9clks/cycle's from the calculation of the number of clocks. But, because =
they=20
are 3clks and 4clks respectively by the theory value, it will able to be =
said=20
that a transfer rate doesn't rise that much, too. (Bus idol time is =
long.) Time=20
loss in the HOST-PCI bridge thinks this a cause. However, PCI is =
designed so=20
that the best performance may appear in the burst transfer. It is =
inevitable=20
that performance is poor in the single transfer.</P>
<P>And, there is a difference in the speed which is near to the double =
in 16bit=20
access and 8bit access in ISA bus. As for this, an I/O cycle is reduced =
when=20
device responds as a 16 bit device in the ISA bus. It is good when even =
a 8bit=20
device is made to operate -IOCS16 when it wants to increse a speed in =
ISA=20
bus.</P></DIV>
<DIV class=3Dpara>
<H3>Notes</H3><IMG class=3Drset height=3D200 alt=3DTesting...=20
src=3D"http://elm-chan.org/works/pci/pci_test.jpeg" width=3D320>=20
<P>How was this report? PCI which it seemed to be complicated and which =
it=20
didn't step into easily could be used with a means like an amateur, too. =
Though=20
it seems generally to be complicated, you may have found that it =
operates based=20
on the simple process surprisingly</P></DIV>
<P class=3Dfoot><IMG alt=3DSign=20
src=3D"http://elm-chan.org/p/sign.png"></P></BODY></HTML>

------=_NextPart_000_0027_01C4EC68.402ECF60
Content-Type: image/png
Content-Transfer-Encoding: base64
Content-Location: http://elm-chan.org/p/header.png

iVBORw0KGgoAAAANSUhEUgAAAZAAAAAbCAMAAABlYSlRAAAAwFBMVEX////8BIT8FIz8RKT8bKz8
dLT8fLT8lLz8nMT8vMwAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAYw5buAAAAAXRSTlMAQObYZgAAAn9JREFUeNrtmW12rCAMhpEgH6ti/7u6BFAIIOoZ+uea
9MyMAlKbp0neiUKwsbG9tl1Rs0K488SVdQbP9+ZijYOanbjSrJHbtklj0fZtAxxTGxrYap2zsKXZ
ysKlUlt24mIk6NYjDmQ60jjmmoVIxJAACas4PtYbVM53UP7323UuAFEk3YUBjo/1pmq/gjshdQuR
Ul1GTLhw/7LnfH71E8F+yFkDv2J6cl0ohXojm0XAQN5MPDIne7/qtl6k6AGyMsoBBiJ8evkUGmUi
nfg0/YZPAaLqqFFdbrMYFLacyq8DianJR+fnH0Fe4px9FTHFrzCAVIWNRmElDyLKwUCLfS9CaiD+
jAqf372oxif7jGQWSDmAVOU2iIU8R47Rn5dZPRDiYZ8Tmp9HR48KZZYEAFkV8qHMglhwcuRYNZQD
X60hmUypIUVrzWrIMHSOgqGlNHOZlSYSEaeGcoCt8/i8BhFrZZZRc5mVklmqG0ASW7OloKfN5PCu
xvvc/AkXs1cDF7/r4XZ+mV1FiO8q+H4ns8JbJqIoEDH8HH4MK5of7zMvfxen/mrg5nZutvN/FUMj
IPJaCxOZlUqOznCKzGIgP9YicjCSr1cyK2W4IIAt6WYxkJVkFJWvsZ/VyCwL5XsKKi0NtOvCQFYC
ofJVSdfLLKiAxJ4JUDnAQFYCofI1PRikMsuBq4BgXVc0sTGQlUBMBSQ8NoQjjZXWFiQ4oI6ik2pO
7GYZBrIWSH6Kqw0aNqt0xBKf7CYLcLCDZfBLoUkgEJqLF4ZnJJaBLAWyU0Ntq5uxPWqq80g4DBB3
zjKQxfp33VYM5Od+/tpugJ/1TGZXPmxTPOqkvLur59txZ+5/tn/4RcoZmlgnCAAAAABJRU5ErkJg
gg==

------=_NextPart_000_0027_01C4EC68.402ECF60
Content-Type: image/png
Content-Transfer-Encoding: base64
Content-Location: http://elm-chan.org/works/pci/pci_logo.png

iVBORw0KGgoAAAANSUhEUgAABQwAAAGUBAMAAACCTnIMAAAAMFBMVEX////8BAQMDAw8PDz/JiZb
W1v8RET8dHR8fHwAAAD8vLzs1dX87Oz89PT///8AAAA9ZFCjAAAAAXRSTlMAQObYZgAAGlxJREFU
eNrtXVtrW1cWVu261ZtTEBLEyWAIhbxJRATypvolgU4zmObFb46hJDCNhxpKDE5tRE3Ab/kNhmEC
aWIIDFOIk0CgpJBIgoBpIJEEhWECtmSMhMFvGt0c67L2OVvS3uesvc/3lRaa6Hb2+c66fHuttUMh
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAPAV4Q2Dgdvn821Pq/o992oWoJJMqluRQGBMzcLPqvo9qZo9OHcpbaBZ8uU3T6pZ
cWW/PV6zC9U57rRbTyZTDmb9oiexhiInqOz31OxD5RJP/l1LDhJmXNTKRjVOsKJscWpW4twcLwYm
h3Q6yTlNLluNEzxU9XPGa5aCi0kMr18YNczQYRfVLPIBs4yJJfwn4t2kqohXcfIVZkbDyVoNRNSD
dcUixEWFTFTkBBOQDeVc86wlHFTMRMiGXgs4Pshydy9wD3knodfY7pnXNUux59KQDY00iF4mxhe8
uKBZHk6wCtmQZYQ44VWMU5njYH0gG3J0zBNeBtqjWUToNf7gvF0kHDH5gmzoFw41x4R+SA5fQjZE