📄 elm - pci pio board.mht
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Subject: ELM - PCI PIO Board
Date: Mon, 27 Dec 2004 23:03:16 +0800
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<DIV class=3Dheader>
<P class=3Dhdh><A href=3D"http://elm-chan.org/"><IMG height=3D27 =
alt=3D"ELM Home Page"=20
src=3D"http://elm-chan.org/p/header.png" width=3D400></A></P>
<H1>An Experiment to Build a PCI Board</H1>
<P class=3Dhdd>September 28, 1997<BR>Last update: January 6, 2001</P>
<HR class=3Dhds>
</DIV>
<DIV class=3Dabst><IMG class=3Drset height=3D101 alt=3D"PCI LOGO"=20
src=3D"http://elm-chan.org/works/pci/pci_logo.png" width=3D323>=20
<P>PCI is a defact standard bus by present local bus for microcomputer =
system,=20
and all PCs are adopting the PCI bus. However, though only this is =
familiar, it=20
never almost sees the experiment which it made use of the PCI bus for. =
The PCI=20
seems to be thought that it cannot be touch in the hand of amateurs due =
to the=20
high performance of the PCI.</P>
<P>Actually, it will unable to build the PCI board that has a function =
which=20
satisfied the PCI standard with only standard logic ICs. But, the PCI is =
complicated as a whole system, however, as for the basic part, it =
operates with=20
very simple protocol. Therefore, it is possible that a PCI board to =
operate only=20
as a target device uses small-scale PLD and it is made. But, the PCI =
board which=20
was done like this and which was built is not a complete PCI device, so =
that it=20
doesn't always operate any systems. This is the experiment to understand =
the=20
operation of PCI persistently. The PCI board to be built is simple=20
PIO.</P></DIV>
<DIV class=3Dpara>
<H3>The Basic Bus Cycles</H3>
<H4>Write Cycle</H4><IMG class=3Drset height=3D260=20
src=3D"http://elm-chan.org/works/pci/pci_time1.png" width=3D320>=20
<P>This is the simplest bus cycle. Target devices detect the start of =
the bus=20
cycle by the FRAME# is asserted at the second clock. At a bus cycle is=20
initiated, the bus comand and the address is taken in to each target =
device=20
attached to the bus, and a terget device which detects the cycle is for =
oneself=20
asserts DEVSEL# to answer to the bus cycle. In this case, because the =
target=20
device answers by the one clock, it is high-speed decoding. When the =
device=20
answers by second or third clock, it is midium or slow decoding.</P>
<P>After the terget device answered with DEVSEL#, the terget device =
confirms=20
IRDY# is asserted (Write data is valid.), and takes data in the target =
device.=20
At the same time, the target device knows that the transfer is the last =
cycle=20
because of FRAME# is deasserted and IRDY# is asserted whitch means =
current data=20
is last transfer.</P>
<P>When the last data is taken in, the terget device drives DEVSEL# and =
TRDY# to=20
be deasserted, and DEVSEL# and TRDY# are released at the next clock, and =
the=20
target device finishes the bus cycle.</P><BR class=3Dclr>
<H4>Read Cycle</H4><IMG class=3Drset height=3D260=20
src=3D"http://elm-chan.org/works/pci/pci_time4.png" width=3D370>=20
<P>This is the simplest read cycle. As for the lead cycle, it needs one =
clock of=20
buffer cycle because the agents who drive the AD bus is changed. =
Therefore, read=20
cycle is compared in write cycle, and one clock much should be=20
necessary.<BR>Target devices detect the start of the bus cycle by the =
FRAME# is=20
asserted at the second clock. At a bus cycle is initiated, the bus =
comand and=20
the address is taken in to each target device attached to the bus, and a =
terget=20
device which detects the cycle is for oneself asserts DEVSEL# to answer =
to the=20
bus cycle. In this case, because the target device answers by the two =
clock, it=20
is midium-speed decoding. It is necessary to put data on the bus at the =
1 clock=20
rest to change the agent for who not to do care and who takes a drive in =
the AD=20
bus even if it answers by high-speed decoding.</P>
<P>After two clocks from start of the bus cycle, terget device puts read =
data on=20
the AD bus, and assert TRDY#. At the next clock, terget device checks =
IRDY#. If=20
the IRDY# is asserted (initiater can accept read data.), the data =
transfer is=20
completed. And FRAME# is deasserted, it means current data is last =
transfer.=20
Terget device detects it and terminates the bus transaction.</P>
<P>After last data is transferred, terget device drives DEVSEL# and =
TRDY# to=20
deassert, and DEVSEL# and TRDY# are released at the next clock, and the =
bus=20
transaction is terminated.</P><BR class=3Dclr>
<H4>Write Cycle (Burst Transfer)</H4><IMG class=3Drset height=3D260=20
src=3D"http://elm-chan.org/works/pci/pci_time3.png" width=3D460>=20
<P>Burst transfer isn't distinguished from the single transfer. The =
terget=20
device checks FRAME# at every data transfer. If the FRAME# keeps being =
asserted,=20
terget device recoginizes next data to be transferred follows. The burst =
transfer is realized with this. The burst transfer is mainly applied to =
memory=20
access, however, it can also be applied to I/O access.</P>
<P>PCI is designed to show performance most at burst transfer. It can be =
imagined easily from the address and data as well being multiplexed. At =
the=20
burst transfer, terget address is only specified at start of data =
transfer is=20
sufficient. PCI reduces the number of signal lines by this, and also =
reduces the=20
stability of the operation and a cost.</P><BR class=3Dclr>
<H4>Fast Back to Back Transaction</H4><IMG class=3Drset height=3D260=20
src=3D"http://elm-chan.org/works/pci/pci_time2.png" width=3D410>=20
<P>The method of first back to back transaction is defined to use a bus=20
efficiently.</P>
<P>Usually, one clock of idol cycle exists between the bus cycles =
(transaction)=20
at least. The idol cycle is a buffer time to prevent each output from =
colliding,=20
however, it can be omitted when device switching is not occured between =
the bus=20
cycles.</P></DIV>
<DIV class=3Dpara>
<H3>The Operation of the I/O Board : STATE</H3>
<P>Because PCI is a complete synchronous bus, all operations are based =
on the=20
system clock. The concept of <B>state machine</B> that a command from =
initiater=20
is executed is necessary in a PCI board (target device) to be built. =
This I/O=20
board realize the state machine with only one SPLD (GAL22V10). Next, =
let's make=20
the value of state counter and the correspondence of the operation a =
figure, and=20
explain.</P><IMG class=3Drset height=3D420 alt=3D"State diagram"=20
src=3D"http://elm-chan.org/works/pci/pci_state.png" width=3D320>=20
<H4>STATE 4</H4>
<P>Bus is in idol. The beginning of the new bus cycle is detected in =
this=20
condition. It transits in STATE 2 or STATE 5 when an I/O cycle is =
initiated to=20
this target device. It transits in STATE 0 when a bus cycle with no =
relations=20
with this target device begins.</P>
<H4>STATE 0</H4>
<P>Bus is in non-idol. Any other transaction is executed. Wait until a =
bus=20
becomes idol condition. It doesn't transit in the new cycle from this =
state.</P>
<H4>STATE 2</H4>
<P>An I/O write cycle to this device is being executed. This device =
asserts=20
DEVSEL# and responds bus cycle. At the same time, terget device asserts =
TRDY#=20
and shows that can accept data to be written. At this time, it latches =
data and=20
transits to STATE 3 when IRDY# is being asserted (initiater can accept =
read=20
data) and FRAME# is being deasserted (last data).</P>
<H4>STATE 3</H4>
<P>DEVSEL# and TRDY# is deasserted. Normaly, DEVSEL# and TRDY# are =
released at=20
the next clock, and transits in the idol state (STATE 0). But, it =
transits=20
directly in STATE 2 or STATE 5 without passing through the idol state =
when it=20
faced this device under this state and I/O read/write command was issued =
again.=20
(fast back to back transaction)</P>
<H4>STATE 5</H4>
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