bidir.v
来自「verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.」· Verilog 代码 · 共 20 行
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20 行
module bidir (bidir_bus, direction_sig, use_bidir_sig);
inout [7:0] bidir_bus;
input direction_sig;
output [7:0] use_bidir_sig;
reg [7:0] output_bus;
wire [7:0] bidir_input;
// When direction_sig is true, output_bus drives the
// bidir_bus port pins.
// The bidir_bus signals are accessible inside the design
// on the bidir_input bus.
// Output part, MUX form.
assign bidir_bus = direction_sig ? output_bus : 8'bz;
// Input part.
assign bidir_input = bidir_bus;
assign use_bidir_sig = bidir_input;
endmodule
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