and_or.scr

veilog 代码 用户可以直接调用

#         (C) Copyright 1991 - 1997 Exemplar Logic, Inc.  All Rights Reserved.
#
#
#                                      NOTICE
#
#          This file belongs to Exemplar Logic, Inc.  It is
#          considered trade secret and is not to be divulged or used by
#          parties who have not received written authorization from
#          the owner.
#
############ Project Settings ############
set process "3"
set part "4010xlPQ100"
set dont_lock_lcells "FALSE"
set input2output "1073741824.000000"
set input2register "1073741824.000000"
set register2output "1073741824.000000"
set register2register "1073741824.000000"
set wire_table "4013xl-3_avg"
set encoding "auto"
set edif_function_property "EQN"
set edif_eqn_or "+"
set edif_eqn_and "*"
set edif_eqn_not "~"
set edif_eqn_not_is_prefix "TRUE"
set modgen_select "auto"
set optimize_timing_cpu_limit "0"

if ![is_var_set dont_restore_design] {
###### Loading technology libraries #######
    load_library xi4xl
}