and_or.lsp

veilog 代码 用户可以直接调用

[WindowState]
WindowPos=2,3,3000,3000,-1,-1,102,72,921,648
ReportWindowPos=2,3,-1,-1,-4,-23,0,0,197,307
CommandLinePercentage=0x0000003E
Document-0=0,1,-1,-1,-4,-23,22,22,421,478
Document Name-0=C:\Verilog\SourceCode\edgetrig.v
Document-1=0,1,-1,-1,-4,-23,44,44,443,500
Document Name-1=C:\Verilog\SourceCode\shifter.v
Document-2=0,1,-1,-1,-4,-23,66,66,465,522
Document Name-2=C:\Verilog\SourceCode\eq_test.v
Document-3=0,1,-1,-1,-4,-23,88,88,487,544
Document Name-3=C:\Verilog\SourceCode\and_or.v
Open Documents=0x00000004
ViewStatusBar=0x00000001

[System]
CWD=C:\Verilog\SourceCode

[Verilog]
Parameters=
Top Module=
Full Case=0x00000000
Parallel Case=0x00000000

[VHDL]
Top Module=
Arch=
Generic=
VHDL Style=0x00000000

[XNF]
Preserve Dangle=0x00000000
Preserve GSR=0x00000000
Preserve GTS=0x00000000
Preserve Pin Loc=0x00000001
Input 2 Output=

[SDF]
SDF Hierarchy=0x00000000
SDF Type=0x00000001

[EDIF]
Design=

[Verilog Out]
Allow Busses=0x00000001

[VHDL Out]
Write Vector Type=std_logic_vector
Allow Busses=0x00000001
Write Bit Type=std_logic
VHDL Write Style=0x00000000

[SDF Out]
SDF Name Style=0x00000000
Write Flat Netlist=0x00000000

[EDIF Out]
Gnd=GND
Power=VCC
Allow Busses=0x00000001
PwrNGnd Is Net=0x00000000
Write Dont Touch=0x00000000

[Files]
InputFileCount=1
InputFile0=C:\Verilog\SourceCode\and_or.v;work;0;Undetermined;
OutputFile=C:\Verilog\SourceCode\and_or.edf
analyze_only=0x00000000
OutputFormat=0x00000000
WriteCnstrntFile=0x00000001
PreProcess=0x00000001
WriteTopOnly=0x00000000
Downto=0x00000000

[File Options]
no opt=

[RunTime]
Optimization=0x00000001
Report=0x00000001
Preserve Hier=0x00000002
Resource Sharing=0x00000001
Run Type=0x00000000
Max Delay=0x00000000
Max Area=0x00000000
CPU Limit=0x00000000
Extended=0x00000000
Pass 1=0x00000001
Pass 2=0x00000001
Pass 3=0x00000001
Pass 4=0x00000001
SingleLevel=0x00000000
OTSingleLevel=0x00000000
OTForce=0x00000000
Break Combo=0x00000000
Convert 3 State=0x00000000
No Wire Table=0x00000000
Transform SR=0x00000001
Bubble Tristates=0x00000001
Run Timing Opt=0x00000001
Replication for Timing=0x00000000
Replication Fanout Limit=0x00000010
Autodissolve Limit=0x00000BB8
Asic Autodissolve Limit=0x0000001E

[FSM]
Encoding=0x00000004

[Report Opts]
Path Detail=0x00000000
Analysis Mode=0x00000000
Wire Tree=0x00000000
Max Slack=0
Max Arr=0
Wire Table=
Break Comb=0x00000000
CD in ID=0x00000000
Do Not Wire=0x00000000
From Paths=
To Paths=
Through Paths=
Not Through Paths=
Path Numbers=1
No Intern Terminal=0x00000000
No IO Terminal=0x00000000
Report Input=0x00000000
Report Net=0x00000000
Show Clock=0x00000001
Sort by Delay=0x00000000
Show Schematic=0x00000000
Report File=

[ReportArea]
Filename=
CellUsage=0x00000001
Hierarchy=0x00000000
Leafs=0x00000001

[Modgen]
Operators=0x00000000
Clock Enable=0x00000001
Counters=0x00000001
Decoders=0x00000001
Modgen On=0x00000001
RAM=0x00000001
ROM=0x00000001
ExtendedMachFlow=0x00000000

[Xilinx PnR]
Bitgen File=
Exec Type=0x00000000
Use Bitfile=0x00000000
Use time file=0x00000000
Use bitgen=0x00000000
Back anotate=0x00000001
Effort=0x00000000
Simulation Output Format=

[Altera Pnr]
Fast IO=0x00000000
Implement EAB=0x00000000
Overright ACF=0x00000000
Register Packing=0x00000000
Run Max=0x00000001
Run Max GUI=0x00000000
Run SetupHold=0x00000002
Setup Max=0x00000001
Timing Analysis=0x00000001
Input to Output Delay=0x00000000
Simulation Output Format=EDIF

[Quartus Pnr]
Run Quartus=0x00000001
Run Quartus GUI=0x00000000
Simulation Output Format=EDIF

[Vantis Pnr]
Run Design Direct=0x00000001
Run Design Direct GUI=0x00000001

[Elab]
Generics=
Params=
WorkLib=
TopOnly=0x00000000

[Device]
Speed=0x00000002
Part=0x0000000A
Package=0x00000000
Preference File=
Max PT=
Max FanOut=
Max Fanout Actel=16
Max FanIn=
LUT Max FanOut=
Max CapLoad=
Global SR=
Exclude GatesCount=0
CIM=
BTW=
Include Gates=
Process=
Voltage=
Temperature=
Fd1s3ix=0x00000000
Fd1s1j=0x00000000
Fd1s3jx=0x00000000
Fd1s1i=0x00000000
Fd1p3jz=0x00000000
Fd1p3iz=0x00000000
Fl1p3jz=0x00000000
Fl1p3iz=0x00000000
Pack Logic to CLB=0x00000000
Map HMAP Sym=0x00000001
Write HBLKNM=0x00000000
Use Fast=0x00000000
Use F5MAPSYM=0x00000000
Quad Clock Buffers=0x00000000
Map LUT=0x00000001
Map IO Reg=0x00000001
Map Complex IO=0x00000001
Map Clock Buffers=0x00000001
Map Cascades=0x00000001
Lock LCells=0x00000001
Write EQN=0x00000001
Wtite F5Map=0x00000001
Write FMAP=0x00000001
Write FMAPSYM=0x00000001
Write OrcaLUT=0x00000001
AutoGSR=0x00000001
ManGSR=0x00000000
Infer 6LUT=0x00000000
Generate TimeSpec=0x00000000
DoLogicRepl=0x00000001
AddIOPads=0x00000001
Map IOB Registers=0x00000000
EdifWriteArrays=0x00000000
Map MUXF5=0x00000001
Map MUXF6=0x00000001
Add ClockBufs=0x00000001
Current Manufacturer=Xilinx
Current Family=4000XL

[Global Constraints]
Clock Freq=
Clock Per=
Input Port 2 Register=
Register 2 Register=
Register 2 Output=
Which Group=0x00000000