mcs_51.map.summary

程序主要用硬件描述语言（VHDL）实现： 单片机与FPGA接口通信的问题

Flow Status : Successful - Sat Aug 13 15:32:41 2005
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : mcs_51
Top-level Entity Name : MCS_51_CPLD
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 45
Total pins : 46
Total memory bits : 0
Total PLLs : 0