read_lie.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

library ieee;--列扫描接受程序：

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_lie is
       port(clk: in std_logic;
            --q_in :  in STD_LOGIC_VECTOR(4 DOWNTO 0);--记数结果
            cnt_in :  in  STD_LOGIC_VECTOR(1 DOWNTO 0);--键盘扫描行号
            lie_scan:  in  STD_LOGIC_VECTOR(3 DOWNTO 0);--列扫描信号
            led:  out integer range 0 to 15 );
end read_lie;
 
architecture behav of read_lie is
   signal cnt: std_logic_vector(1 downto 0);
   --signal zlie: std_logic_vector(1 downto 0);--列扫描信号转换
begin
  process(clk,cnt_in,lie_scan)
  begin
    cnt <= cnt_in;
  if(clk'event and clk = '1') then
      if(cnt=0) then
        if(lie_scan="1110") then
            led <= 0;
        elsif(lie_scan="1101") then
            led <= 1;
        elsif(lie_scan="1011") then
            led <= 2;
        elsif(lie_scan="0111") then
            led <= 3;
        else
            null;
        end if;
       end if;
     
    if(cnt=1) then
       if(lie_scan="1110") then
           led <= 4;
       elsif(lie_scan="1101") then
           led <= 5;
       elsif(lie_scan="1011") then
           led <= 6;
       elsif(lie_scan="0111") then
           led <= 7;
       else
           null;
       end if;
    end if;

    if(cnt=2) then
       if(lie_scan="1110") then
           led <= 8;
       elsif(lie_scan="1101") then
           led <= 9;
       elsif(lie_scan="1011") then
           led <= 10;
       elsif(lie_scan="0111") then
           led <= 11;
       else
           null;
       end if;
    end if;
    if(cnt=3) then
        if(lie_scan="1110") then
            led <= 12;
        elsif(lie_scan="1101") then
            led <= 13;
        elsif(lie_scan="1011") then
            led <= 14;
        elsif(lie_scan="0111") then
            led <= 15;
        else
            null;
        end if;
    end if;
end if;
end process;
end behav;