📄 key_scan.tan.qmsg

📁 程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描
💻 QMSG
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{ "Info" "ITDB_TSU_RESULT" "FPGA_S51_0:inst5\|latch_address\[0\] p0 ALE 5.400 ns register " "Info: tsu for register \"FPGA_S51_0:inst5\|latch_address\[0\]\" (data pin = \"p0\", clock pin = \"ALE\") is 5.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest pin register " "Info: + Longest pin to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns p0 1 PIN PIN_47 5 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_47; Fanout = 5; PIN Node = 'p0'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { p0 } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 48 328 496 64 "p\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.900 ns) 8.000 ns FPGA_S51_0:inst5\|latch_address\[0\] 2 REG LC3_B2 4 " "Info: 2: + IC(4.000 ns) + CELL(0.900 ns) = 8.000 ns; Loc. = LC3_B2; Fanout = 4; REG Node = 'FPGA_S51_0:inst5\|latch_address\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "4.900 ns" { p0 FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 50.00 % " "Info: Total cell delay = 4.000 ns ( 50.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 50.00 % " "Info: Total interconnect delay = 4.000 ns ( 50.00 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "8.000 ns" { p0 FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { p0 p0~out FPGA_S51_0:inst5|latch_address[0] } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.100ns 0.900ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"ALE\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns ALE 1 CLK PIN_126 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'ALE'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { ALE } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 88 328 496 104 "ALE" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns FPGA_S51_0:inst5\|latch_address\[0\] 2 REG LC3_B2 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_B2; Fanout = 4; REG Node = 'FPGA_S51_0:inst5\|latch_address\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.000 ns" { ALE FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { ALE FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { ALE ALE~out FPGA_S51_0:inst5|latch_address[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "8.000 ns" { p0 FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "8.000 ns" { p0 p0~out FPGA_S51_0:inst5|latch_address[0] } { 0.000ns 0.000ns 4.000ns } { 0.000ns 3.100ns 0.900ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { ALE FPGA_S51_0:inst5|latch_address[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { ALE ALE~out FPGA_S51_0:inst5|latch_address[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock scan\[0\] Keyboard:inst\|SCN\[0\] 16.600 ns register " "Info: tco from clock \"clock\" to destination pin \"scan\[0\]\" through register \"Keyboard:inst\|SCN\[0\]\" is 16.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 9.600 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 9.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clock 1 CLK PIN_125 15 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { clock } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 120 8 176 136 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.900 ns) 4.800 ns Keyboard:inst\|Clock_1\[14\] 2 REG LC1_C16 8 " "Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_C16; Fanout = 8; REG Node = 'Keyboard:inst\|Clock_1\[14\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.900 ns" { clock Keyboard:inst|Clock_1[14] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.000 ns) 9.600 ns Keyboard:inst\|SCN\[0\] 3 REG LC2_C6 1 " "Info: 3: + IC(4.800 ns) + CELL(0.000 ns) = 9.600 ns; Loc. = LC2_C6; Fanout = 1; REG Node = 'Keyboard:inst\|SCN\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "4.800 ns" { Keyboard:inst|Clock_1[14] Keyboard:inst|SCN[0] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 29.17 % " "Info: Total cell delay = 2.800 ns ( 29.17 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.800 ns 70.83 % " "Info: Total interconnect delay = 6.800 ns ( 70.83 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "9.600 ns" { clock Keyboard:inst|Clock_1[14] Keyboard:inst|SCN[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { clock clock~out Keyboard:inst|Clock_1[14] Keyboard:inst|SCN[0] } { 0.000ns 0.000ns 2.000ns 4.800ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.100 ns + Longest register pin " "Info: + Longest register to pin delay is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Keyboard:inst\|SCN\[0\] 1 REG LC2_C6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C6; Fanout = 1; REG Node = 'Keyboard:inst\|SCN\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { Keyboard:inst|SCN[0] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.900 ns) 6.100 ns scan\[0\] 2 PIN PIN_81 0 " "Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'scan\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "6.100 ns" { Keyboard:inst|SCN[0] scan[0] } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 344 472 648 360 "scan\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 63.93 % " "Info: Total cell delay = 3.900 ns ( 63.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 36.07 % " "Info: Total interconnect delay = 2.200 ns ( 36.07 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "6.100 ns" { Keyboard:inst|SCN[0] scan[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.100 ns" { Keyboard:inst|SCN[0] scan[0] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } } }  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "9.600 ns" { clock Keyboard:inst|Clock_1[14] Keyboard:inst|SCN[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "9.600 ns" { clock clock~out Keyboard:inst|Clock_1[14] Keyboard:inst|SCN[0] } { 0.000ns 0.000ns 2.000ns 4.800ns } { 0.000ns 1.900ns 0.900ns 0.000ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "6.100 ns" { Keyboard:inst|SCN[0] scan[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "6.100 ns" { Keyboard:inst|SCN[0] scan[0] } { 0.000ns 2.200ns } { 0.000ns 3.900ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "FPGA_S51_0:inst5\|latch_address\[6\] p6 ALE 0.900 ns register " "Info: th for register \"FPGA_S51_0:inst5\|latch_address\[6\]\" (data pin = \"p6\", clock pin = \"ALE\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ALE destination 3.900 ns + Longest register " "Info: + Longest clock path from clock \"ALE\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns ALE 1 CLK PIN_126 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'ALE'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { ALE } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 88 328 496 104 "ALE" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns FPGA_S51_0:inst5\|latch_address\[6\] 2 REG LC2_B10 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B10; Fanout = 1; REG Node = 'FPGA_S51_0:inst5\|latch_address\[6\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.000 ns" { ALE FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { ALE FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { ALE ALE~out FPGA_S51_0:inst5|latch_address[6] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns p6 1 PIN PIN_56 5 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_56; Fanout = 5; PIN Node = 'p6'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { p6 } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 48 328 496 64 "p\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.900 ns) 4.400 ns FPGA_S51_0:inst5\|latch_address\[6\] 2 REG LC2_B10 1 " "Info: 2: + IC(1.600 ns) + CELL(0.900 ns) = 4.400 ns; Loc. = LC2_B10; Fanout = 1; REG Node = 'FPGA_S51_0:inst5\|latch_address\[6\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.500 ns" { p6 FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 63.64 % " "Info: Total cell delay = 2.800 ns ( 63.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 36.36 % " "Info: Total interconnect delay = 1.600 ns ( 36.36 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "4.400 ns" { p6 FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "4.400 ns" { p6 p6~out FPGA_S51_0:inst5|latch_address[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { ALE FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { ALE ALE~out FPGA_S51_0:inst5|latch_address[6] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "4.400 ns" { p6 FPGA_S51_0:inst5|latch_address[6] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "4.400 ns" { p6 p6~out FPGA_S51_0:inst5|latch_address[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 17:48:46 2005 " "Info: Processing ended: Wed Aug 10 17:48:46 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}
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