key_scan.tan.qmsg

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 64 328 496 80 "WR" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 88 328 496 104 "ALE" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 120 8 176 136 "clock" "" } } } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Keyboard:inst\|Clock_1\[14\] " "Info: Detected ripple clock \"Keyboard:inst\|Clock_1\[14\]\" as buffer" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } } { "e:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Keyboard:inst\|Clock_1\[14\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WR " "Info: No valid register-to-register data paths exist for clock \"WR\"" {  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ALE " "Info: No valid register-to-register data paths exist for clock \"ALE\"" {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register Keyboard:inst\|Clock_1\[4\] register Keyboard:inst\|Clock_1\[0\] 74.07 MHz 13.5 ns Internal " "Info: Clock \"clock\" has Internal fmax of 74.07 MHz between source register \"Keyboard:inst\|Clock_1\[4\]\" and destination register \"Keyboard:inst\|Clock_1\[0\]\" (period= 13.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.300 ns + Longest register register " "Info: + Longest register to register delay is 11.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Keyboard:inst\|Clock_1\[4\] 1 REG LC4_C17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C17; Fanout = 3; REG Node = 'Keyboard:inst\|Clock_1\[4\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { Keyboard:inst|Clock_1[4] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 2.500 ns Keyboard:inst\|reduce_nor~129 2 COMB LC1_C17 1 " "Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC1_C17; Fanout = 1; COMB Node = 'Keyboard:inst\|reduce_nor~129'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.500 ns" { Keyboard:inst|Clock_1[4] Keyboard:inst|reduce_nor~129 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.400 ns) 5.600 ns Keyboard:inst\|reduce_nor~130 3 COMB LC7_C16 6 " "Info: 3: + IC(1.700 ns) + CELL(1.400 ns) = 5.600 ns; Loc. = LC7_C16; Fanout = 6; COMB Node = 'Keyboard:inst\|reduce_nor~130'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.100 ns" { Keyboard:inst|reduce_nor~129 Keyboard:inst|reduce_nor~130 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.900 ns) 8.100 ns Keyboard:inst\|reduce_nor~131 4 COMB LC2_C16 1 " "Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 8.100 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'Keyboard:inst\|reduce_nor~131'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.500 ns" { Keyboard:inst|reduce_nor~130 Keyboard:inst|reduce_nor~131 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 11.300 ns Keyboard:inst\|Clock_1\[0\] 5 REG LC2_C13 3 " "Info: 5: + IC(1.800 ns) + CELL(1.400 ns) = 11.300 ns; Loc. = LC2_C13; Fanout = 3; REG Node = 'Keyboard:inst\|Clock_1\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.200 ns" { Keyboard:inst|reduce_nor~131 Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns 58.41 % " "Info: Total cell delay = 6.600 ns ( 58.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 41.59 % " "Info: Total interconnect delay = 4.700 ns ( 41.59 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "11.300 ns" { Keyboard:inst|Clock_1[4] Keyboard:inst|reduce_nor~129 Keyboard:inst|reduce_nor~130 Keyboard:inst|reduce_nor~131 Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "11.300 ns" { Keyboard:inst|Clock_1[4] Keyboard:inst|reduce_nor~129 Keyboard:inst|reduce_nor~130 Keyboard:inst|reduce_nor~131 Keyboard:inst|Clock_1[0] } { 0.000ns 0.600ns 1.700ns 0.600ns 1.800ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.400ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clock 1 CLK PIN_125 15 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { clock } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 120 8 176 136 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns Keyboard:inst\|Clock_1\[0\] 2 REG LC2_C13 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C13; Fanout = 3; REG Node = 'Keyboard:inst\|Clock_1\[0\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.000 ns" { clock Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clock 1 CLK PIN_125 15 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "" { clock } "NODE_NAME" } "" } } { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 120 8 176 136 "clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns Keyboard:inst\|Clock_1\[4\] 2 REG LC4_C17 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C17; Fanout = 3; REG Node = 'Keyboard:inst\|Clock_1\[4\]'" {  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "2.000 ns" { clock Keyboard:inst|Clock_1[4] } "NODE_NAME" } "" } } { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[4] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[4] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "Keyboard.vhd" "" { Text "F:/EDA/KEY_SCAN/Keyboard.vhd" 27 -1 0 } }  } 0}  } { { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "11.300 ns" { Keyboard:inst|Clock_1[4] Keyboard:inst|reduce_nor~129 Keyboard:inst|reduce_nor~130 Keyboard:inst|reduce_nor~131 Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "11.300 ns" { Keyboard:inst|Clock_1[4] Keyboard:inst|reduce_nor~129 Keyboard:inst|reduce_nor~130 Keyboard:inst|reduce_nor~131 Keyboard:inst|Clock_1[0] } { 0.000ns 0.600ns 1.700ns 0.600ns 1.800ns } { 0.000ns 1.900ns 1.400ns 1.900ns 1.400ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[0] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" "" { Report "F:/EDA/KEY_SCAN/db/KEY_SCAN_cmp.qrpt" Compiler "KEY_SCAN" "UNKNOWN" "V1" "F:/EDA/KEY_SCAN/db/KEY_SCAN.quartus_db" { Floorplan "F:/EDA/KEY_SCAN/" "" "3.900 ns" { clock Keyboard:inst|Clock_1[4] } "NODE_NAME" } "" } } { "e:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus42/bin/Technology_Viewer.qrui" "3.900 ns" { clock clock~out Keyboard:inst|Clock_1[4] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}