key_scan.map.qmsg

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[1\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[1\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|p0_1\[0\]~reg0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|p0_1\[0\]~reg0\" register" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|p0_1\[0\]~reg0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|p0_1\[0\]~reg0\" with stuck clock port to stuck value GND" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~0 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~0\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~0 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~0\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~2 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~2\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~2 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~2\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~4 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~4\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~4 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~4\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~6 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~6\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~6 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~6\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~8 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~8\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~8 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~8\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~10 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~10\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~10 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~10\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~12 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~12\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~12 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~12\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_NO_CLOCK_TRANSITION" "FPGA_S51_0:inst5\|process2~14 " "Warning: No clock transition on \"FPGA_S51_0:inst5\|process2~14\" register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "FPGA_S51_0:inst5\|process2~14 clock GND " "Warning: Reduced register \"FPGA_S51_0:inst5\|process2~14\" with stuck clock port to stuck value GND" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "e:/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_DISABLED_OE" "" "Warning: TRI or OPNDRN buffers permanently disabled" { { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[7\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[7\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[6\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[6\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[5\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[5\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[4\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[4\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[3\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[3\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[2\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[2\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[1\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[1\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0} { "Warning" "WOPT_MLS_NODE_NAME" "FPGA_S51_0:inst5\|p0_1\[0\] " "Warning: Node \"FPGA_S51_0:inst5\|p0_1\[0\]\"" {  } { { "fpga_s51_0.vhd" "" { Text "F:/EDA/KEY_SCAN/fpga_s51_0.vhd" 19 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "kin\[3\] " "Warning: No output dependent on input pin \"kin\[3\]\"" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 136 8 176 152 "kin\[3..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "kin\[2\] " "Warning: No output dependent on input pin \"kin\[2\]\"" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 136 8 176 152 "kin\[3..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "kin\[1\] " "Warning: No output dependent on input pin \"kin\[1\]\"" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 136 8 176 152 "kin\[3..0\]" "" } } } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "kin\[0\] " "Warning: No output dependent on input pin \"kin\[0\]\"" {  } { { "key_scan_lie.bdf" "" { Schematic "F:/EDA/KEY_SCAN/key_scan_lie.bdf" { { 136 8 176 152 "kin\[3..0\]" "" } } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "15 " "Info: Implemented 15 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "44 " "Info: Implemented 44 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "86 " "Info: Implemented 86 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 54 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 54 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 10 17:48:34 2005 " "Info: Processing ended: Wed Aug 10 17:48:34 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}