key_scan.hier_info

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

|key_scan_lie
DATAOUT1[0] <= FPGA_S51_0:inst5.dataout1[0]
DATAOUT1[1] <= FPGA_S51_0:inst5.dataout1[1]
DATAOUT1[2] <= FPGA_S51_0:inst5.dataout1[2]
DATAOUT1[3] <= FPGA_S51_0:inst5.dataout1[3]
DATAOUT1[4] <= FPGA_S51_0:inst5.dataout1[4]
DATAOUT1[5] <= FPGA_S51_0:inst5.dataout1[5]
DATAOUT1[6] <= FPGA_S51_0:inst5.dataout1[6]
DATAOUT1[7] <= FPGA_S51_0:inst5.dataout1[7]
WR => FPGA_S51_0:inst5.wr
ALE => FPGA_S51_0:inst5.ale
clock => Keyboard:inst.clk
kin[0] => Keyboard:inst.KIN[0]
kin[1] => Keyboard:inst.KIN[1]
kin[2] => Keyboard:inst.KIN[2]
kin[3] => Keyboard:inst.KIN[3]
p7 => FPGA_S51_0:inst5.p0[7]
p6 => FPGA_S51_0:inst5.p0[6]
p5 => FPGA_S51_0:inst5.p0[5]
p4 => FPGA_S51_0:inst5.p0[4]
p3 => FPGA_S51_0:inst5.p0[3]
p2 => FPGA_S51_0:inst5.p0[2]
p1 => FPGA_S51_0:inst5.p0[1]
p0 => FPGA_S51_0:inst5.p0[0]
DATAOUT2[0] <= FPGA_S51_0:inst5.dataout2[0]
DATAOUT2[1] <= FPGA_S51_0:inst5.dataout2[1]
DATAOUT2[2] <= FPGA_S51_0:inst5.dataout2[2]
DATAOUT2[3] <= FPGA_S51_0:inst5.dataout2[3]
DATAOUT2[4] <= FPGA_S51_0:inst5.dataout2[4]
DATAOUT2[5] <= FPGA_S51_0:inst5.dataout2[5]
DATAOUT2[6] <= FPGA_S51_0:inst5.dataout2[6]
DATAOUT2[7] <= FPGA_S51_0:inst5.dataout2[7]
DATAOUT3[0] <= FPGA_S51_0:inst5.dataout3[0]
DATAOUT3[1] <= FPGA_S51_0:inst5.dataout3[1]
DATAOUT3[2] <= FPGA_S51_0:inst5.dataout3[2]
DATAOUT3[3] <= FPGA_S51_0:inst5.dataout3[3]
DATAOUT3[4] <= FPGA_S51_0:inst5.dataout3[4]
DATAOUT3[5] <= FPGA_S51_0:inst5.dataout3[5]
DATAOUT3[6] <= FPGA_S51_0:inst5.dataout3[6]
DATAOUT3[7] <= FPGA_S51_0:inst5.dataout3[7]
DATAOUT4[0] <= FPGA_S51_0:inst5.dataout4[0]
DATAOUT4[1] <= FPGA_S51_0:inst5.dataout4[1]
DATAOUT4[2] <= FPGA_S51_0:inst5.dataout4[2]
DATAOUT4[3] <= FPGA_S51_0:inst5.dataout4[3]
DATAOUT4[4] <= FPGA_S51_0:inst5.dataout4[4]
DATAOUT4[5] <= FPGA_S51_0:inst5.dataout4[5]
DATAOUT4[6] <= FPGA_S51_0:inst5.dataout4[6]
DATAOUT4[7] <= FPGA_S51_0:inst5.dataout4[7]
P07 <= FPGA_S51_0:inst5.p0_1[7]
P06 <= FPGA_S51_0:inst5.p0_1[6]
P05 <= FPGA_S51_0:inst5.p0_1[5]
P04 <= FPGA_S51_0:inst5.p0_1[4]
P03 <= FPGA_S51_0:inst5.p0_1[3]
P02 <= FPGA_S51_0:inst5.p0_1[2]
P01 <= FPGA_S51_0:inst5.p0_1[1]
P00 <= FPGA_S51_0:inst5.p0_1[0]
scan[0] <= Keyboard:inst.ScanSignal[0]
scan[1] <= Keyboard:inst.ScanSignal[1]
scan[2] <= Keyboard:inst.ScanSignal[2]
scan[3] <= Keyboard:inst.ScanSignal[3]


|key_scan_lie|FPGA_S51_0:inst5
p0[0] => latch_address[0].DATAIN
p0[0] => dataout1[0]~reg0.DATAIN
p0[0] => dataout2[0]~reg0.DATAIN
p0[0] => dataout3[0]~reg0.DATAIN
p0[0] => dataout4[0]~reg0.DATAIN
p0[1] => latch_address[1].DATAIN
p0[1] => dataout1[1]~reg0.DATAIN
p0[1] => dataout2[1]~reg0.DATAIN
p0[1] => dataout3[1]~reg0.DATAIN
p0[1] => dataout4[1]~reg0.DATAIN
p0[2] => latch_address[2].DATAIN
p0[2] => dataout1[2]~reg0.DATAIN
p0[2] => dataout2[2]~reg0.DATAIN
p0[2] => dataout3[2]~reg0.DATAIN
p0[2] => dataout4[2]~reg0.DATAIN
p0[3] => latch_address[3].DATAIN
p0[3] => dataout1[3]~reg0.DATAIN
p0[3] => dataout2[3]~reg0.DATAIN
p0[3] => dataout3[3]~reg0.DATAIN
p0[3] => dataout4[3]~reg0.DATAIN
p0[4] => latch_address[4].DATAIN
p0[4] => dataout1[4]~reg0.DATAIN
p0[4] => dataout2[4]~reg0.DATAIN
p0[4] => dataout3[4]~reg0.DATAIN
p0[4] => dataout4[4]~reg0.DATAIN
p0[5] => latch_address[5].DATAIN
p0[5] => dataout1[5]~reg0.DATAIN
p0[5] => dataout2[5]~reg0.DATAIN
p0[5] => dataout3[5]~reg0.DATAIN
p0[5] => dataout4[5]~reg0.DATAIN
p0[6] => latch_address[6].DATAIN
p0[6] => dataout1[6]~reg0.DATAIN
p0[6] => dataout2[6]~reg0.DATAIN
p0[6] => dataout3[6]~reg0.DATAIN
p0[6] => dataout4[6]~reg0.DATAIN
p0[7] => latch_address[7].DATAIN
p0[7] => dataout1[7]~reg0.DATAIN
p0[7] => dataout2[7]~reg0.DATAIN
p0[7] => dataout3[7]~reg0.DATAIN
p0[7] => dataout4[7]~reg0.DATAIN
wr => dataout1[6]~reg0.CLK
wr => dataout1[5]~reg0.CLK
wr => dataout1[4]~reg0.CLK
wr => dataout1[3]~reg0.CLK
wr => dataout1[2]~reg0.CLK
wr => dataout1[1]~reg0.CLK
wr => dataout1[0]~reg0.CLK
wr => dataout2[7]~reg0.CLK
wr => dataout2[6]~reg0.CLK
wr => dataout2[5]~reg0.CLK
wr => dataout2[4]~reg0.CLK
wr => dataout2[3]~reg0.CLK
wr => dataout2[2]~reg0.CLK
wr => dataout2[1]~reg0.CLK
wr => dataout2[0]~reg0.CLK
wr => dataout3[7]~reg0.CLK
wr => dataout3[6]~reg0.CLK
wr => dataout3[5]~reg0.CLK
wr => dataout3[4]~reg0.CLK
wr => dataout3[3]~reg0.CLK
wr => dataout3[2]~reg0.CLK
wr => dataout3[1]~reg0.CLK
wr => dataout3[0]~reg0.CLK
wr => dataout4[7]~reg0.CLK
wr => dataout4[6]~reg0.CLK
wr => dataout4[5]~reg0.CLK
wr => dataout4[4]~reg0.CLK
wr => dataout4[3]~reg0.CLK
wr => dataout4[2]~reg0.CLK
wr => dataout4[1]~reg0.CLK
wr => dataout4[0]~reg0.CLK
wr => dataout1[7]~reg0.CLK
rd => p0_1[6]~reg0.CLK
rd => p0_1[5]~reg0.CLK
rd => p0_1[4]~reg0.CLK
rd => p0_1[3]~reg0.CLK
rd => p0_1[2]~reg0.CLK
rd => p0_1[1]~reg0.CLK
rd => p0_1[0]~reg0.CLK
rd => process2~0.CLK
rd => process2~2.CLK
rd => process2~4.CLK
rd => process2~6.CLK
rd => process2~8.CLK
rd => process2~10.CLK
rd => process2~12.CLK
rd => process2~14.CLK
rd => p0_1[7]~reg0.CLK
ale => latch_address[6].CLK
ale => latch_address[5].CLK
ale => latch_address[4].CLK
ale => latch_address[3].CLK
ale => latch_address[2].CLK
ale => latch_address[1].CLK
ale => latch_address[0].CLK
ale => latch_address[7].CLK
datain1[0] => Select~8.IN0
datain1[1] => Select~7.IN0
datain1[2] => Select~6.IN0
datain1[3] => Select~5.IN0
datain1[4] => Select~4.IN0
datain1[5] => Select~3.IN0
datain1[6] => Select~2.IN0
datain1[7] => Select~0.IN0
datain2[0] => Select~8.IN1
datain2[1] => Select~7.IN1
datain2[2] => Select~6.IN1
datain2[3] => Select~5.IN1
datain2[4] => Select~4.IN1
datain2[5] => Select~3.IN1
datain2[6] => Select~2.IN1
datain2[7] => Select~0.IN1
datain3[0] => Select~8.IN2
datain3[1] => Select~7.IN2
datain3[2] => Select~6.IN2
datain3[3] => Select~5.IN2
datain3[4] => Select~4.IN2
datain3[5] => Select~3.IN2
datain3[6] => Select~2.IN2
datain3[7] => Select~0.IN2
datain4[0] => Select~8.IN3
datain4[1] => Select~7.IN3
datain4[2] => Select~6.IN3
datain4[3] => Select~5.IN3
datain4[4] => Select~4.IN3
datain4[5] => Select~3.IN3
datain4[6] => Select~2.IN3
datain4[7] => Select~0.IN3
datain5[0] => Select~8.IN4
datain5[1] => Select~7.IN4
datain5[2] => Select~6.IN4
datain5[3] => Select~5.IN4
datain5[4] => Select~4.IN4
datain5[5] => Select~3.IN4
datain5[6] => Select~2.IN4
datain5[7] => Select~0.IN4
datain6[0] => Select~8.IN5
datain6[1] => Select~7.IN5
datain6[2] => Select~6.IN5
datain6[3] => Select~5.IN5
datain6[4] => Select~4.IN5
datain6[5] => Select~3.IN5
datain6[6] => Select~2.IN5
datain6[7] => Select~0.IN5
datain7[0] => Select~8.IN6
datain7[1] => Select~7.IN6
datain7[2] => Select~6.IN6
datain7[3] => Select~5.IN6
datain7[4] => Select~4.IN6
datain7[5] => Select~3.IN6
datain7[6] => Select~2.IN6
datain7[7] => Select~0.IN6
datain8[0] => Select~8.IN7
datain8[1] => Select~7.IN7
datain8[2] => Select~6.IN7
datain8[3] => Select~5.IN7
datain8[4] => Select~4.IN7
datain8[5] => Select~3.IN7
datain8[6] => Select~2.IN7
datain8[7] => Select~0.IN7
dataout1[0] <= dataout1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[1] <= dataout1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[2] <= dataout1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[3] <= dataout1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[4] <= dataout1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[5] <= dataout1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[6] <= dataout1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout1[7] <= dataout1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
p0_1[0] <= process2~16.DB_MAX_OUTPUT_PORT_TYPE
p0_1[1] <= process2~15.DB_MAX_OUTPUT_PORT_TYPE
p0_1[2] <= process2~13.DB_MAX_OUTPUT_PORT_TYPE
p0_1[3] <= process2~11.DB_MAX_OUTPUT_PORT_TYPE
p0_1[4] <= process2~9.DB_MAX_OUTPUT_PORT_TYPE
p0_1[5] <= process2~7.DB_MAX_OUTPUT_PORT_TYPE
p0_1[6] <= process2~5.DB_MAX_OUTPUT_PORT_TYPE
p0_1[7] <= process2~3.DB_MAX_OUTPUT_PORT_TYPE
dataout2[0] <= dataout2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[1] <= dataout2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[2] <= dataout2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[3] <= dataout2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[4] <= dataout2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[5] <= dataout2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[6] <= dataout2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout2[7] <= dataout2[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[0] <= dataout3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[1] <= dataout3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[2] <= dataout3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[3] <= dataout3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[4] <= dataout3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[5] <= dataout3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[6] <= dataout3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout3[7] <= dataout3[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[0] <= dataout4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[1] <= dataout4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[2] <= dataout4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[3] <= dataout4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[4] <= dataout4[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[5] <= dataout4[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[6] <= dataout4[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dataout4[7] <= dataout4[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|key_scan_lie|pailie:inst2
enter => a.CLK
enter => data5[6]~reg0.CLK
enter => data5[5]~reg0.CLK
enter => data5[4]~reg0.CLK
enter => data5[3]~reg0.CLK
enter => data5[2]~reg0.CLK
enter => data5[1]~reg0.CLK
enter => data5[0]~reg0.CLK
enter => data4[7]~reg0.CLK
enter => data4[6]~reg0.CLK
enter => data4[5]~reg0.CLK
enter => data4[4]~reg0.CLK
enter => data4[3]~reg0.CLK
enter => data4[2]~reg0.CLK
enter => data4[1]~reg0.CLK
enter => data4[0]~reg0.CLK
enter => data3[7]~reg0.CLK
enter => data3[6]~reg0.CLK
enter => data3[5]~reg0.CLK
enter => data3[4]~reg0.CLK
enter => data3[3]~reg0.CLK
enter => data3[2]~reg0.CLK
enter => data3[1]~reg0.CLK
enter => data3[0]~reg0.CLK
enter => data2[7]~reg0.CLK
enter => data2[6]~reg0.CLK