out_hang2.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--****************************************
ENTITY OUT_HANG2 is
           PORT(
CLK  :  IN  STD_LOGIC;
--系统时钟脉冲
--Q_OUT  :  OUT  STD_LOGIC_VECTOR(10 DOWNTO 0);
--记数结果
CNT_OUT  :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
--键盘扫描信号
CLK_SCAN  :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
--扫描序列
                );
END OUT_HANG2;
--***********************************
ARCHITECTURE a OF OUT_HANG2 is
 SIGNAL  Q      :   STD_LOGIC_VECTOR(10 DOWNTO 0);
 SIGNAL  CNT,S  :   STD_LOGIC_VECTOR(1 DOWNTO 0);
 SIGNAL  SEL    :   STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
 PROCESS(CLK)
 BEGIN
IF CLK'EVENT AND CLK='1' THEN
   Q<=Q+1;
END IF;
 END PROCESS;
       CNT<=Q(10 DOWNTO 9);
       -- CNT<=Q(4 DOWNTO 3);       
       SEL<="1110"  WHEN  S=0 ELSE
            "1101"  WHEN  S=1 ELSE
            "1011"  WHEN  S=2 ELSE
            "0111"  WHEN  S=3 ELSE
            "1111";
--CONNECTION 信号连接
S<=CNT;
CNT_OUT<=CNT;
--Q_OUT<=Q;
CLK_SCAN<=SEL;
END a;