key_scan.fit.eqn

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

--D1_dataout1[7] is FPGA_S51_0:inst5|dataout1[7] at LC2_B20
--operation mode is normal

D1_dataout1[7]_lut_out = p7;
D1_dataout1[7] = DFFEA(D1_dataout1[7]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[6] is FPGA_S51_0:inst5|dataout1[6] at LC7_B20
--operation mode is normal

D1_dataout1[6]_lut_out = p6;
D1_dataout1[6] = DFFEA(D1_dataout1[6]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[5] is FPGA_S51_0:inst5|dataout1[5] at LC2_B19
--operation mode is normal

D1_dataout1[5]_lut_out = p5;
D1_dataout1[5] = DFFEA(D1_dataout1[5]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[4] is FPGA_S51_0:inst5|dataout1[4] at LC8_B12
--operation mode is normal

D1_dataout1[4]_lut_out = p4;
D1_dataout1[4] = DFFEA(D1_dataout1[4]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[3] is FPGA_S51_0:inst5|dataout1[3] at LC3_B13
--operation mode is normal

D1_dataout1[3]_lut_out = p3;
D1_dataout1[3] = DFFEA(D1_dataout1[3]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[2] is FPGA_S51_0:inst5|dataout1[2] at LC1_B12
--operation mode is normal

D1_dataout1[2]_lut_out = p2;
D1_dataout1[2] = DFFEA(D1_dataout1[2]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[1] is FPGA_S51_0:inst5|dataout1[1] at LC4_B2
--operation mode is normal

D1_dataout1[1]_lut_out = p1;
D1_dataout1[1] = DFFEA(D1_dataout1[1]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout1[0] is FPGA_S51_0:inst5|dataout1[0] at LC2_B8
--operation mode is normal

D1_dataout1[0]_lut_out = p0;
D1_dataout1[0] = DFFEA(D1_dataout1[0]_lut_out, GLOBAL(WR), , , D1L64, , );


--D1_dataout2[7] is FPGA_S51_0:inst5|dataout2[7] at LC3_B19
--operation mode is normal

D1_dataout2[7]_lut_out = p7;
D1_dataout2[7] = DFFEA(D1_dataout2[7]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[6] is FPGA_S51_0:inst5|dataout2[6] at LC7_B19
--operation mode is normal

D1_dataout2[6]_lut_out = p6;
D1_dataout2[6] = DFFEA(D1_dataout2[6]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[5] is FPGA_S51_0:inst5|dataout2[5] at LC4_B19
--operation mode is normal

D1_dataout2[5]_lut_out = p5;
D1_dataout2[5] = DFFEA(D1_dataout2[5]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[4] is FPGA_S51_0:inst5|dataout2[4] at LC8_B11
--operation mode is normal

D1_dataout2[4]_lut_out = p4;
D1_dataout2[4] = DFFEA(D1_dataout2[4]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[3] is FPGA_S51_0:inst5|dataout2[3] at LC4_B23
--operation mode is normal

D1_dataout2[3]_lut_out = p3;
D1_dataout2[3] = DFFEA(D1_dataout2[3]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[2] is FPGA_S51_0:inst5|dataout2[2] at LC7_B12
--operation mode is normal

D1_dataout2[2]_lut_out = p2;
D1_dataout2[2] = DFFEA(D1_dataout2[2]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[1] is FPGA_S51_0:inst5|dataout2[1] at LC6_B23
--operation mode is normal

D1_dataout2[1]_lut_out = p1;
D1_dataout2[1] = DFFEA(D1_dataout2[1]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout2[0] is FPGA_S51_0:inst5|dataout2[0] at LC1_B23
--operation mode is normal

D1_dataout2[0]_lut_out = p0;
D1_dataout2[0] = DFFEA(D1_dataout2[0]_lut_out, GLOBAL(WR), , , D1L74, , );


--D1_dataout3[7] is FPGA_S51_0:inst5|dataout3[7] at LC1_B19
--operation mode is normal

D1_dataout3[7]_lut_out = p7;
D1_dataout3[7] = DFFEA(D1_dataout3[7]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[6] is FPGA_S51_0:inst5|dataout3[6] at LC5_B19
--operation mode is normal

D1_dataout3[6]_lut_out = p6;
D1_dataout3[6] = DFFEA(D1_dataout3[6]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[5] is FPGA_S51_0:inst5|dataout3[5] at LC6_B19
--operation mode is normal

D1_dataout3[5]_lut_out = p5;
D1_dataout3[5] = DFFEA(D1_dataout3[5]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[4] is FPGA_S51_0:inst5|dataout3[4] at LC2_B12
--operation mode is normal

D1_dataout3[4]_lut_out = p4;
D1_dataout3[4] = DFFEA(D1_dataout3[4]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[3] is FPGA_S51_0:inst5|dataout3[3] at LC1_B24
--operation mode is normal

D1_dataout3[3]_lut_out = p3;
D1_dataout3[3] = DFFEA(D1_dataout3[3]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[2] is FPGA_S51_0:inst5|dataout3[2] at LC6_B12
--operation mode is normal

D1_dataout3[2]_lut_out = p2;
D1_dataout3[2] = DFFEA(D1_dataout3[2]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[1] is FPGA_S51_0:inst5|dataout3[1] at LC1_B2
--operation mode is normal

D1_dataout3[1]_lut_out = p1;
D1_dataout3[1] = DFFEA(D1_dataout3[1]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout3[0] is FPGA_S51_0:inst5|dataout3[0] at LC5_B23
--operation mode is normal

D1_dataout3[0]_lut_out = p0;
D1_dataout3[0] = DFFEA(D1_dataout3[0]_lut_out, GLOBAL(WR), , , D1L84, , );


--D1_dataout4[7] is FPGA_S51_0:inst5|dataout4[7] at LC5_B20
--operation mode is normal

D1_dataout4[7]_lut_out = p7;
D1_dataout4[7] = DFFEA(D1_dataout4[7]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[6] is FPGA_S51_0:inst5|dataout4[6] at LC3_B20
--operation mode is normal

D1_dataout4[6]_lut_out = p6;
D1_dataout4[6] = DFFEA(D1_dataout4[6]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[5] is FPGA_S51_0:inst5|dataout4[5] at LC8_B20
--operation mode is normal

D1_dataout4[5]_lut_out = p5;
D1_dataout4[5] = DFFEA(D1_dataout4[5]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[4] is FPGA_S51_0:inst5|dataout4[4] at LC5_B9
--operation mode is normal

D1_dataout4[4]_lut_out = p4;
D1_dataout4[4] = DFFEA(D1_dataout4[4]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[3] is FPGA_S51_0:inst5|dataout4[3] at LC8_B23
--operation mode is normal

D1_dataout4[3]_lut_out = p3;
D1_dataout4[3] = DFFEA(D1_dataout4[3]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[2] is FPGA_S51_0:inst5|dataout4[2] at LC4_B12
--operation mode is normal

D1_dataout4[2]_lut_out = p2;
D1_dataout4[2] = DFFEA(D1_dataout4[2]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[1] is FPGA_S51_0:inst5|dataout4[1] at LC7_B23
--operation mode is normal

D1_dataout4[1]_lut_out = p1;
D1_dataout4[1] = DFFEA(D1_dataout4[1]_lut_out, GLOBAL(WR), , , D1L94, , );


--D1_dataout4[0] is FPGA_S51_0:inst5|dataout4[0] at LC2_B23
--operation mode is normal

D1_dataout4[0]_lut_out = p0;
D1_dataout4[0] = DFFEA(D1_dataout4[0]_lut_out, GLOBAL(WR), , , D1L94, , );


--B1_SCN[3] is Keyboard:inst|SCN[3] at LC6_C6
--operation mode is normal

B1_SCN[3]_lut_out = !B1_Counter[0] # !B1_Counter[1];
B1_SCN[3] = DFFEA(B1_SCN[3]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--B1_SCN[2] is Keyboard:inst|SCN[2] at LC4_C6
--operation mode is normal

B1_SCN[2]_lut_out = B1_Counter[0] # !B1_Counter[1];
B1_SCN[2] = DFFEA(B1_SCN[2]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--B1_SCN[1] is Keyboard:inst|SCN[1] at LC1_C6
--operation mode is normal

B1_SCN[1]_lut_out = B1_Counter[1] # !B1_Counter[0];
B1_SCN[1] = DFFEA(B1_SCN[1]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--B1_SCN[0] is Keyboard:inst|SCN[0] at LC2_C6
--operation mode is normal

B1_SCN[0]_lut_out = B1_Counter[1] # B1_Counter[0];
B1_SCN[0] = DFFEA(B1_SCN[0]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--D1_latch_address[0] is FPGA_S51_0:inst5|latch_address[0] at LC3_B2
--operation mode is normal

D1_latch_address[0]_lut_out = p0;
D1_latch_address[0] = DFFEA(D1_latch_address[0]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[1] is FPGA_S51_0:inst5|latch_address[1] at LC7_B2
--operation mode is normal

D1_latch_address[1]_lut_out = p1;
D1_latch_address[1] = DFFEA(D1_latch_address[1]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[6] is FPGA_S51_0:inst5|latch_address[6] at LC2_B10
--operation mode is normal

D1_latch_address[6]_lut_out = p6;
D1_latch_address[6] = DFFEA(D1_latch_address[6]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[5] is FPGA_S51_0:inst5|latch_address[5] at LC3_B10
--operation mode is normal

D1_latch_address[5]_lut_out = p5;
D1_latch_address[5] = DFFEA(D1_latch_address[5]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[4] is FPGA_S51_0:inst5|latch_address[4] at LC4_B10
--operation mode is normal

D1_latch_address[4]_lut_out = p4;
D1_latch_address[4] = DFFEA(D1_latch_address[4]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[3] is FPGA_S51_0:inst5|latch_address[3] at LC1_B13
--operation mode is normal

D1_latch_address[3]_lut_out = p3;
D1_latch_address[3] = DFFEA(D1_latch_address[3]_lut_out, !GLOBAL(ALE), , , , , );


--D1L05 is FPGA_S51_0:inst5|reduce_nor~45 at LC5_B10
--operation mode is normal

D1L05 = !D1_latch_address[3] & !D1_latch_address[4] & !D1_latch_address[5] & !D1_latch_address[6];


--D1_latch_address[2] is FPGA_S51_0:inst5|latch_address[2] at LC6_B10
--operation mode is normal

D1_latch_address[2]_lut_out = p2;
D1_latch_address[2] = DFFEA(D1_latch_address[2]_lut_out, !GLOBAL(ALE), , , , , );


--D1_latch_address[7] is FPGA_S51_0:inst5|latch_address[7] at LC7_B10
--operation mode is normal

D1_latch_address[7]_lut_out = p7;
D1_latch_address[7] = DFFEA(D1_latch_address[7]_lut_out, !GLOBAL(ALE), , , , , );


--D1L15 is FPGA_S51_0:inst5|reduce_nor~46 at LC1_B10
--operation mode is normal

D1L15 = !D1_latch_address[7] & !D1_latch_address[2] & D1L05;


--D1L64 is FPGA_S51_0:inst5|reduce_nor~0 at LC5_B2
--operation mode is normal

D1L64 = D1L15 & !D1_latch_address[1] & !D1_latch_address[0];


--D1L74 is FPGA_S51_0:inst5|reduce_nor~1 at LC8_B2
--operation mode is normal

D1L74 = D1L15 & D1_latch_address[0] & !D1_latch_address[1];


--D1L84 is FPGA_S51_0:inst5|reduce_nor~2 at LC2_B2
--operation mode is normal

D1L84 = D1L15 & D1_latch_address[1] & !D1_latch_address[0];


--D1L94 is FPGA_S51_0:inst5|reduce_nor~3 at LC6_B2
--operation mode is normal

D1L94 = D1L15 & D1_latch_address[1] & D1_latch_address[0];


--B1_Counter[0] is Keyboard:inst|Counter[0] at LC3_C6
--operation mode is normal

B1_Counter[0]_lut_out = !B1_Counter[0];
B1_Counter[0] = DFFEA(B1_Counter[0]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--B1_Counter[1] is Keyboard:inst|Counter[1] at LC5_C6
--operation mode is normal

B1_Counter[1]_lut_out = B1_Counter[1] $ B1_Counter[0];
B1_Counter[1] = DFFEA(B1_Counter[1]_lut_out, GLOBAL(B1_Clock_1[14]), , , , , );


--B1_Clock_1[14] is Keyboard:inst|Clock_1[14] at LC1_C16
--operation mode is normal

B1_Clock_1[14]_lut_out = F1_unreg_res_node[14] & B1L32 # B1L12 # B1L02;
B1_Clock_1[14] = DFFEA(B1_Clock_1[14]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[13] is Keyboard:inst|Clock_1[13] at LC4_C19
--operation mode is normal

B1_Clock_1[13]_lut_out = H3_cs_buffer[13];
B1_Clock_1[13] = DFFEA(B1_Clock_1[13]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[12] is Keyboard:inst|Clock_1[12] at LC1_C14
--operation mode is normal

B1_Clock_1[12]_lut_out = H3_cs_buffer[12];
B1_Clock_1[12] = DFFEA(B1_Clock_1[12]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[11] is Keyboard:inst|Clock_1[11] at LC8_C16
--operation mode is normal

B1_Clock_1[11]_lut_out = H3_cs_buffer[11] & B1L32 # B1L12 # B1L02;
B1_Clock_1[11] = DFFEA(B1_Clock_1[11]_lut_out, GLOBAL(clock), , , , , );


--B1L02 is Keyboard:inst|reduce_nor~127 at LC6_C16
--operation mode is normal

B1L02 = B1_Clock_1[12] # B1_Clock_1[13] # !B1_Clock_1[14] # !B1_Clock_1[11];


--B1_Clock_1[8] is Keyboard:inst|Clock_1[8] at LC1_C21
--operation mode is normal

B1_Clock_1[8]_lut_out = H3_cs_buffer[8];
B1_Clock_1[8] = DFFEA(B1_Clock_1[8]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[7] is Keyboard:inst|Clock_1[7] at LC1_C18
--operation mode is normal

B1_Clock_1[7]_lut_out = H3_cs_buffer[7];
B1_Clock_1[7] = DFFEA(B1_Clock_1[7]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[10] is Keyboard:inst|Clock_1[10] at LC5_C16
--operation mode is normal

B1_Clock_1[10]_lut_out = H3_cs_buffer[10] & B1L32 # B1L12 # B1L02;
B1_Clock_1[10] = DFFEA(B1_Clock_1[10]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[9] is Keyboard:inst|Clock_1[9] at LC4_C16
--operation mode is normal

B1_Clock_1[9]_lut_out = H3_cs_buffer[9] & B1L32 # B1L12 # B1L02;
B1_Clock_1[9] = DFFEA(B1_Clock_1[9]_lut_out, GLOBAL(clock), , , , , );


--B1L12 is Keyboard:inst|reduce_nor~128 at LC3_C16
--operation mode is normal

B1L12 = B1_Clock_1[7] # B1_Clock_1[8] # !B1_Clock_1[10] # !B1_Clock_1[9];


--B1_Clock_1[6] is Keyboard:inst|Clock_1[6] at LC6_C17
--operation mode is normal

B1_Clock_1[6]_lut_out = H3_cs_buffer[6];
B1_Clock_1[6] = DFFEA(B1_Clock_1[6]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[4] is Keyboard:inst|Clock_1[4] at LC4_C17
--operation mode is normal

B1_Clock_1[4]_lut_out = H3_cs_buffer[4];
B1_Clock_1[4] = DFFEA(B1_Clock_1[4]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[3] is Keyboard:inst|Clock_1[3] at LC3_C17
--operation mode is normal

B1_Clock_1[3]_lut_out = H3_cs_buffer[3];
B1_Clock_1[3] = DFFEA(B1_Clock_1[3]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[5] is Keyboard:inst|Clock_1[5] at LC5_C17
--operation mode is normal

B1_Clock_1[5]_lut_out = H3_cs_buffer[5] & B1L32 # B1L12 # B1L02;
B1_Clock_1[5] = DFFEA(B1_Clock_1[5]_lut_out, GLOBAL(clock), , , , , );


--B1L22 is Keyboard:inst|reduce_nor~129 at LC1_C17
--operation mode is normal

B1L22 = B1_Clock_1[3] # B1_Clock_1[4] # B1_Clock_1[6] # !B1_Clock_1[5];


--B1_Clock_1[2] is Keyboard:inst|Clock_1[2] at LC1_C13
--operation mode is normal

B1_Clock_1[2]_lut_out = H3_cs_buffer[2];
B1_Clock_1[2] = DFFEA(B1_Clock_1[2]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[1] is Keyboard:inst|Clock_1[1] at LC2_C17
--operation mode is normal

B1_Clock_1[1]_lut_out = H3_cs_buffer[1];
B1_Clock_1[1] = DFFEA(B1_Clock_1[1]_lut_out, GLOBAL(clock), , , , , );


--B1_Clock_1[0] is Keyboard:inst|Clock_1[0] at LC2_C13
--operation mode is arithmetic

B1_Clock_1[0]_lut_out = B1L42 & !B1_Clock_1[0];
B1_Clock_1[0] = DFFEA(B1_Clock_1[0]_lut_out, GLOBAL(clock), , , , , );

--H3_cout[0] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0] at LC2_C13
--operation mode is arithmetic

H3_cout[0] = CARRY(B1_Clock_1[0]);


--B1L32 is Keyboard:inst|reduce_nor~130 at LC7_C16
--operation mode is normal

B1L32 = B1_Clock_1[0] # B1_Clock_1[1] # B1_Clock_1[2] # B1L22;


--H3_cs_buffer[13] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC7_C15
--operation mode is arithmetic

H3_cs_buffer[13] = B1_Clock_1[13] $ H3_cout[12];

--H3_cout[13] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13] at LC7_C15
--operation mode is arithmetic

H3_cout[13] = CARRY(B1_Clock_1[13] & H3_cout[12]);


--F1_unreg_res_node[14] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[14] at LC8_C15
--operation mode is normal