key_scan.map.rpt

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

; alt_mercury_add_sub.inc          ; yes             ; e:/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; aglobal42.inc                    ; yes             ; e:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; addcore.tdf                      ; yes             ; e:/altera/quartus42/libraries/megafunctions/addcore.tdf             ;
; a_csnbuffer.inc                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc         ;
; a_csnbuffer.tdf                  ; yes             ; e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf         ;
; altshift.tdf                     ; yes             ; e:/altera/quartus42/libraries/megafunctions/altshift.tdf            ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 86      ;
; Total combinational functions     ; 36      ;
; Total 4-input functions           ; 10      ;
; Total 3-input functions           ; 6       ;
; Total 2-input functions           ; 6       ;
; Total 1-input functions           ; 14      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 61      ;
; Total logic cells in carry chains ; 15      ;
; I/O pins                          ; 59      ;
; Maximum fan-out node              ; WR      ;
; Maximum fan-out                   ; 32      ;
; Total fan-out                     ; 277     ;
; Average fan-out                   ; 1.91    ;
+-----------------------------------+---------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 0     ;
; Number of synthesis-generated cells                    ; 86    ;
; Number of WYSIWYG LUTs                                 ; 0     ;
; Number of synthesis-generated LUTs                     ; 36    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 61    ;
; Number of cells with combinational logic only          ; 25    ;
; Number of cells with registers only                    ; 50    ;
; Number of cells with combinational logic and registers ; 11    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 61    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Aug 10 17:48:29 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off KEY_SCAN -c KEY_SCAN
Info: Found 1 design units, including 1 entities, in source file key_scan_lie.bdf
    Info: Found entity 1: key_scan_lie
Info: Found 2 design units, including 1 entities, in source file pailie.vhd
    Info: Found design unit 1: pailie-rtl
    Info: Found entity 1: pailie
Info: Found 2 design units, including 1 entities, in source file Keyboard.vhd
    Info: Found design unit 1: Keyboard-Scan
    Info: Found entity 1: Keyboard
Info: Found 2 design units, including 1 entities, in source file fpga_s51_0.vhd
    Info: Found design unit 1: FPGA_S51_0-behav
    Info: Found entity 1: FPGA_S51_0
Warning: Block or symbol "Keyboard" of instance "inst" overlaps another block or symbol
Warning: Found multiple base names
Warning: Found multiple base names
Warning: VHDL Process Statement warning at pailie.vhd(33): signal "b" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Tied undriven net "data[7]" at pailie.vhd(16) to GND or VCC
Warning: Tied undriven net "data[6]" at pailie.vhd(16) to GND or VCC
Warning: Tied undriven net "data[5]" at pailie.vhd(16) to GND or VCC
Warning: Tied undriven net "data[4]" at pailie.vhd(16) to GND or VCC
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[7]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[7]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[6]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[6]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[5]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[5]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[4]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[4]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[3]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[3]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[2]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[2]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[1]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[1]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|p0_1[0]~reg0" register
Warning: Reduced register "FPGA_S51_0:inst5|p0_1[0]~reg0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~0" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~0" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~2" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~2" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~4" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~4" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~6" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~6" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~8" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~8" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~10" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~10" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~12" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~12" with stuck clock port to stuck value GND
Warning: No clock transition on "FPGA_S51_0:inst5|process2~14" register
Warning: Reduced register "FPGA_S51_0:inst5|process2~14" with stuck clock port to stuck value GND
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus42/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: TRI or OPNDRN buffers permanently disabled
    Warning: Node "FPGA_S51_0:inst5|p0_1[7]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[6]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[5]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[4]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[3]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[2]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[1]"
    Warning: Node "FPGA_S51_0:inst5|p0_1[0]"
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "kin[3]"
    Warning: No output dependent on input pin "kin[2]"
    Warning: No output dependent on input pin "kin[1]"
    Warning: No output dependent on input pin "kin[0]"
Info: Implemented 145 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 44 output pins
    Info: Implemented 86 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 54 warnings
    Info: Processing ended: Wed Aug 10 17:48:34 2005
    Info: Elapsed time: 00:00:05