key_scan.tan.rpt

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

; N/A           ; None        ; -2.000 ns ; p4   ; FPGA_S51_0:inst5|latch_address[4] ; ALE      ;
; N/A           ; None        ; -2.100 ns ; p0   ; FPGA_S51_0:inst5|dataout2[0]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p0   ; FPGA_S51_0:inst5|dataout3[0]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p0   ; FPGA_S51_0:inst5|dataout4[0]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p3   ; FPGA_S51_0:inst5|dataout1[3]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p3   ; FPGA_S51_0:inst5|latch_address[3] ; ALE      ;
; N/A           ; None        ; -2.100 ns ; p4   ; FPGA_S51_0:inst5|dataout1[4]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p4   ; FPGA_S51_0:inst5|dataout2[4]      ; WR       ;
; N/A           ; None        ; -2.100 ns ; p4   ; FPGA_S51_0:inst5|dataout3[4]      ; WR       ;
; N/A           ; None        ; -2.300 ns ; p2   ; FPGA_S51_0:inst5|dataout1[2]      ; WR       ;
; N/A           ; None        ; -2.300 ns ; p2   ; FPGA_S51_0:inst5|latch_address[2] ; ALE      ;
; N/A           ; None        ; -2.300 ns ; p2   ; FPGA_S51_0:inst5|dataout2[2]      ; WR       ;
; N/A           ; None        ; -2.300 ns ; p2   ; FPGA_S51_0:inst5|dataout3[2]      ; WR       ;
; N/A           ; None        ; -2.300 ns ; p2   ; FPGA_S51_0:inst5|dataout4[2]      ; WR       ;
; N/A           ; None        ; -2.400 ns ; p3   ; FPGA_S51_0:inst5|dataout2[3]      ; WR       ;
; N/A           ; None        ; -2.400 ns ; p3   ; FPGA_S51_0:inst5|dataout3[3]      ; WR       ;
; N/A           ; None        ; -2.400 ns ; p3   ; FPGA_S51_0:inst5|dataout4[3]      ; WR       ;
; N/A           ; None        ; -2.500 ns ; p0   ; FPGA_S51_0:inst5|dataout1[0]      ; WR       ;
; N/A           ; None        ; -2.700 ns ; p0   ; FPGA_S51_0:inst5|latch_address[0] ; ALE      ;
+---------------+-------------+-----------+------+-----------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Wed Aug 10 17:48:45 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off KEY_SCAN -c KEY_SCAN
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "WR" is an undefined clock
    Info: Assuming node "ALE" is an undefined clock
    Info: Assuming node "clock" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "Keyboard:inst|Clock_1[14]" as buffer
Info: No valid register-to-register data paths exist for clock "WR"
Info: No valid register-to-register data paths exist for clock "ALE"
Info: Clock "clock" has Internal fmax of 74.07 MHz between source register "Keyboard:inst|Clock_1[4]" and destination register "Keyboard:inst|Clock_1[0]" (period= 13.5 ns)
    Info: + Longest register to register delay is 11.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C17; Fanout = 3; REG Node = 'Keyboard:inst|Clock_1[4]'
        Info: 2: + IC(0.600 ns) + CELL(1.900 ns) = 2.500 ns; Loc. = LC1_C17; Fanout = 1; COMB Node = 'Keyboard:inst|reduce_nor~129'
        Info: 3: + IC(1.700 ns) + CELL(1.400 ns) = 5.600 ns; Loc. = LC7_C16; Fanout = 6; COMB Node = 'Keyboard:inst|reduce_nor~130'
        Info: 4: + IC(0.600 ns) + CELL(1.900 ns) = 8.100 ns; Loc. = LC2_C16; Fanout = 1; COMB Node = 'Keyboard:inst|reduce_nor~131'
        Info: 5: + IC(1.800 ns) + CELL(1.400 ns) = 11.300 ns; Loc. = LC2_C13; Fanout = 3; REG Node = 'Keyboard:inst|Clock_1[0]'
        Info: Total cell delay = 6.600 ns ( 58.41 % )
        Info: Total interconnect delay = 4.700 ns ( 41.59 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C13; Fanout = 3; REG Node = 'Keyboard:inst|Clock_1[0]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
        Info: - Longest clock path from clock "clock" to source register is 3.900 ns
            Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'
            Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_C17; Fanout = 3; REG Node = 'Keyboard:inst|Clock_1[4]'
            Info: Total cell delay = 1.900 ns ( 48.72 % )
            Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Micro setup delay of destination is 1.300 ns
Info: tsu for register "FPGA_S51_0:inst5|latch_address[0]" (data pin = "p0", clock pin = "ALE") is 5.400 ns
    Info: + Longest pin to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_47; Fanout = 5; PIN Node = 'p0'
        Info: 2: + IC(4.000 ns) + CELL(0.900 ns) = 8.000 ns; Loc. = LC3_B2; Fanout = 4; REG Node = 'FPGA_S51_0:inst5|latch_address[0]'
        Info: Total cell delay = 4.000 ns ( 50.00 % )
        Info: Total interconnect delay = 4.000 ns ( 50.00 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock "ALE" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'ALE'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_B2; Fanout = 4; REG Node = 'FPGA_S51_0:inst5|latch_address[0]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock "clock" to destination pin "scan[0]" through register "Keyboard:inst|SCN[0]" is 16.600 ns
    Info: + Longest clock path from clock "clock" to source register is 9.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 15; CLK Node = 'clock'
        Info: 2: + IC(2.000 ns) + CELL(0.900 ns) = 4.800 ns; Loc. = LC1_C16; Fanout = 8; REG Node = 'Keyboard:inst|Clock_1[14]'
        Info: 3: + IC(4.800 ns) + CELL(0.000 ns) = 9.600 ns; Loc. = LC2_C6; Fanout = 1; REG Node = 'Keyboard:inst|SCN[0]'
        Info: Total cell delay = 2.800 ns ( 29.17 % )
        Info: Total interconnect delay = 6.800 ns ( 70.83 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C6; Fanout = 1; REG Node = 'Keyboard:inst|SCN[0]'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_81; Fanout = 0; PIN Node = 'scan[0]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: th for register "FPGA_S51_0:inst5|latch_address[6]" (data pin = "p6", clock pin = "ALE") is 0.900 ns
    Info: + Longest clock path from clock "ALE" to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_126; Fanout = 8; CLK Node = 'ALE'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_B10; Fanout = 1; REG Node = 'FPGA_S51_0:inst5|latch_address[6]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 4.400 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_56; Fanout = 5; PIN Node = 'p6'
        Info: 2: + IC(1.600 n