pailie.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

Library IEEE;
Use IEEE.Std_Logic_1164.All;
Use IEEE.Std_Logic_Unsigned.All;

Entity pailie Is
Port
   (enter,ci:in std_logic;
    data_bcd:in std_logic_vector(3 downto 0);
    data1,data2,data3,data4,data5,data6,data7,data8:out std_logic_vector(7 downto 0)
   );
end pailie;

architecture rtl of pailie is
signal a:std_logic;
signal b,c:integer range 0 to 4;
signal data:std_logic_vector(7 downto 0);
signal data1_0,data2_0,data3_0,data4_0,data5_0:std_logic_vector(7 downto 0);

begin
data(3 downto 0)<=data_bcd;
  process(enter)
    begin
      if rising_edge(enter) then
         a<=not a;
      end if;
  end process;

  process(ci,enter)
   begin
   if(enter='0')then
        b<=0;
     else
       c<=b;
      if rising_edge(ci) then
        data5_0<=data4_0;
        data4_0<=data3_0;
        data3_0<=data2_0;
        data2_0<=data1_0;
        data1_0<=data;
        b<=b+1;
        c<=b;
      end if;
   end if;
   --end if;
  end process;

  process(enter)
    begin
     if falling_edge(enter) then
        if(a='1')then
           case c is
            when 1=> data5<="00000000";
                     data4<="00000000";
                     data3<="00000000";
                     data2<="00000000";
                     data1<=data1_0;
                     --b<=0;
            when 2=> data5<="00000000";
                     data4<="00000000";
                     data3<="00000000";
                     data2<=data2_0;
                     data1<=data1_0;
                     --b<=0;
            when 3=> data5<="00000000";
                     data4<="00000000";
                     data3<=data3_0;
                     data2<=data2_0;
                     data1<=data1_0;
                     --b<=0; 
            when 4=> data5<="00000000";
                     data4<=data4_0;
                     data3<=data3_0;
                     data2<=data2_0;
                     data1<=data1_0;
                     --b<=0; 
            when others=>data5<=data5_0;
                     data4<=data4_0;
                     data3<=data3_0;
                     data2<=data2_0;
                     data1<=data1_0;
                     --b<=0;
         end case;
        else
         case c is
            when 1=> data8<="00000000";
                     data7<="00000000";
                     data6<=data1_0;
                     --b<=0;
            when 2=> data8<="00000000";
                     data7<=data2_0;
                     data6<=data1_0;
                     --b<=0;
            when others=>data8<=data3_0;
                     data7<=data2_0;
                     data6<=data1_0;
                     --b<=0;
          end case;
         end if;
       end if;
  end process;      
end rtl;