out_hang.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity out_hang is
    PORT(
          clk:     IN  STD_LOGIC;--系统时钟脉冲
          --q_out :  OUT  STD_LOGIC_VECTOR(4 DOWNTO 0);--记数结果
        cnt_out :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);--扫描序列
        clk_scan:  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)--键盘扫描信号
         );
END out_hang ;

architecture behav of out_hang is
      signal count: std_logic_vector(4 downto 0);
      signal cnt,s: std_logic_vector(1 downto 0);
      signal sel:   STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
 process(clk)
 begin
   if(clk'event and clk = '1') then
               count<= count +1;
   end if;
 end process;

 cnt<=count(4 DOWNTO 3);
 sel <=  "1110" when s=0 else
         "1101" when s=1 else
         "1011" when s=2 else
         "0111" when s=3 else
         "1111";
 s <= cnt;
 clk_scan <= sel;
 --q_out <= count;
 cnt_out <= cnt;
end behav;