key_scan.map.eqn

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

--D1_dataout1[7] is FPGA_S51_0:inst5|dataout1[7]
--operation mode is normal

D1_dataout1[7]_lut_out = p7;
D1_dataout1[7] = DFFEA(D1_dataout1[7]_lut_out, WR, , , D1L64, , );


--D1_dataout1[6] is FPGA_S51_0:inst5|dataout1[6]
--operation mode is normal

D1_dataout1[6]_lut_out = p6;
D1_dataout1[6] = DFFEA(D1_dataout1[6]_lut_out, WR, , , D1L64, , );


--D1_dataout1[5] is FPGA_S51_0:inst5|dataout1[5]
--operation mode is normal

D1_dataout1[5]_lut_out = p5;
D1_dataout1[5] = DFFEA(D1_dataout1[5]_lut_out, WR, , , D1L64, , );


--D1_dataout1[4] is FPGA_S51_0:inst5|dataout1[4]
--operation mode is normal

D1_dataout1[4]_lut_out = p4;
D1_dataout1[4] = DFFEA(D1_dataout1[4]_lut_out, WR, , , D1L64, , );


--D1_dataout1[3] is FPGA_S51_0:inst5|dataout1[3]
--operation mode is normal

D1_dataout1[3]_lut_out = p3;
D1_dataout1[3] = DFFEA(D1_dataout1[3]_lut_out, WR, , , D1L64, , );


--D1_dataout1[2] is FPGA_S51_0:inst5|dataout1[2]
--operation mode is normal

D1_dataout1[2]_lut_out = p2;
D1_dataout1[2] = DFFEA(D1_dataout1[2]_lut_out, WR, , , D1L64, , );


--D1_dataout1[1] is FPGA_S51_0:inst5|dataout1[1]
--operation mode is normal

D1_dataout1[1]_lut_out = p1;
D1_dataout1[1] = DFFEA(D1_dataout1[1]_lut_out, WR, , , D1L64, , );


--D1_dataout1[0] is FPGA_S51_0:inst5|dataout1[0]
--operation mode is normal

D1_dataout1[0]_lut_out = p0;
D1_dataout1[0] = DFFEA(D1_dataout1[0]_lut_out, WR, , , D1L64, , );


--D1_dataout2[7] is FPGA_S51_0:inst5|dataout2[7]
--operation mode is normal

D1_dataout2[7]_lut_out = p7;
D1_dataout2[7] = DFFEA(D1_dataout2[7]_lut_out, WR, , , D1L74, , );


--D1_dataout2[6] is FPGA_S51_0:inst5|dataout2[6]
--operation mode is normal

D1_dataout2[6]_lut_out = p6;
D1_dataout2[6] = DFFEA(D1_dataout2[6]_lut_out, WR, , , D1L74, , );


--D1_dataout2[5] is FPGA_S51_0:inst5|dataout2[5]
--operation mode is normal

D1_dataout2[5]_lut_out = p5;
D1_dataout2[5] = DFFEA(D1_dataout2[5]_lut_out, WR, , , D1L74, , );


--D1_dataout2[4] is FPGA_S51_0:inst5|dataout2[4]
--operation mode is normal

D1_dataout2[4]_lut_out = p4;
D1_dataout2[4] = DFFEA(D1_dataout2[4]_lut_out, WR, , , D1L74, , );


--D1_dataout2[3] is FPGA_S51_0:inst5|dataout2[3]
--operation mode is normal

D1_dataout2[3]_lut_out = p3;
D1_dataout2[3] = DFFEA(D1_dataout2[3]_lut_out, WR, , , D1L74, , );


--D1_dataout2[2] is FPGA_S51_0:inst5|dataout2[2]
--operation mode is normal

D1_dataout2[2]_lut_out = p2;
D1_dataout2[2] = DFFEA(D1_dataout2[2]_lut_out, WR, , , D1L74, , );


--D1_dataout2[1] is FPGA_S51_0:inst5|dataout2[1]
--operation mode is normal

D1_dataout2[1]_lut_out = p1;
D1_dataout2[1] = DFFEA(D1_dataout2[1]_lut_out, WR, , , D1L74, , );


--D1_dataout2[0] is FPGA_S51_0:inst5|dataout2[0]
--operation mode is normal

D1_dataout2[0]_lut_out = p0;
D1_dataout2[0] = DFFEA(D1_dataout2[0]_lut_out, WR, , , D1L74, , );


--D1_dataout3[7] is FPGA_S51_0:inst5|dataout3[7]
--operation mode is normal

D1_dataout3[7]_lut_out = p7;
D1_dataout3[7] = DFFEA(D1_dataout3[7]_lut_out, WR, , , D1L84, , );


--D1_dataout3[6] is FPGA_S51_0:inst5|dataout3[6]
--operation mode is normal

D1_dataout3[6]_lut_out = p6;
D1_dataout3[6] = DFFEA(D1_dataout3[6]_lut_out, WR, , , D1L84, , );


--D1_dataout3[5] is FPGA_S51_0:inst5|dataout3[5]
--operation mode is normal

D1_dataout3[5]_lut_out = p5;
D1_dataout3[5] = DFFEA(D1_dataout3[5]_lut_out, WR, , , D1L84, , );


--D1_dataout3[4] is FPGA_S51_0:inst5|dataout3[4]
--operation mode is normal

D1_dataout3[4]_lut_out = p4;
D1_dataout3[4] = DFFEA(D1_dataout3[4]_lut_out, WR, , , D1L84, , );


--D1_dataout3[3] is FPGA_S51_0:inst5|dataout3[3]
--operation mode is normal

D1_dataout3[3]_lut_out = p3;
D1_dataout3[3] = DFFEA(D1_dataout3[3]_lut_out, WR, , , D1L84, , );


--D1_dataout3[2] is FPGA_S51_0:inst5|dataout3[2]
--operation mode is normal

D1_dataout3[2]_lut_out = p2;
D1_dataout3[2] = DFFEA(D1_dataout3[2]_lut_out, WR, , , D1L84, , );


--D1_dataout3[1] is FPGA_S51_0:inst5|dataout3[1]
--operation mode is normal

D1_dataout3[1]_lut_out = p1;
D1_dataout3[1] = DFFEA(D1_dataout3[1]_lut_out, WR, , , D1L84, , );


--D1_dataout3[0] is FPGA_S51_0:inst5|dataout3[0]
--operation mode is normal

D1_dataout3[0]_lut_out = p0;
D1_dataout3[0] = DFFEA(D1_dataout3[0]_lut_out, WR, , , D1L84, , );


--D1_dataout4[7] is FPGA_S51_0:inst5|dataout4[7]
--operation mode is normal

D1_dataout4[7]_lut_out = p7;
D1_dataout4[7] = DFFEA(D1_dataout4[7]_lut_out, WR, , , D1L94, , );


--D1_dataout4[6] is FPGA_S51_0:inst5|dataout4[6]
--operation mode is normal

D1_dataout4[6]_lut_out = p6;
D1_dataout4[6] = DFFEA(D1_dataout4[6]_lut_out, WR, , , D1L94, , );


--D1_dataout4[5] is FPGA_S51_0:inst5|dataout4[5]
--operation mode is normal

D1_dataout4[5]_lut_out = p5;
D1_dataout4[5] = DFFEA(D1_dataout4[5]_lut_out, WR, , , D1L94, , );


--D1_dataout4[4] is FPGA_S51_0:inst5|dataout4[4]
--operation mode is normal

D1_dataout4[4]_lut_out = p4;
D1_dataout4[4] = DFFEA(D1_dataout4[4]_lut_out, WR, , , D1L94, , );


--D1_dataout4[3] is FPGA_S51_0:inst5|dataout4[3]
--operation mode is normal

D1_dataout4[3]_lut_out = p3;
D1_dataout4[3] = DFFEA(D1_dataout4[3]_lut_out, WR, , , D1L94, , );


--D1_dataout4[2] is FPGA_S51_0:inst5|dataout4[2]
--operation mode is normal

D1_dataout4[2]_lut_out = p2;
D1_dataout4[2] = DFFEA(D1_dataout4[2]_lut_out, WR, , , D1L94, , );


--D1_dataout4[1] is FPGA_S51_0:inst5|dataout4[1]
--operation mode is normal

D1_dataout4[1]_lut_out = p1;
D1_dataout4[1] = DFFEA(D1_dataout4[1]_lut_out, WR, , , D1L94, , );


--D1_dataout4[0] is FPGA_S51_0:inst5|dataout4[0]
--operation mode is normal

D1_dataout4[0]_lut_out = p0;
D1_dataout4[0] = DFFEA(D1_dataout4[0]_lut_out, WR, , , D1L94, , );


--B1_SCN[3] is Keyboard:inst|SCN[3]
--operation mode is normal

B1_SCN[3]_lut_out = !B1_Counter[1] # !B1_Counter[0];
B1_SCN[3] = DFFEA(B1_SCN[3]_lut_out, B1_Clock_1[14], , , , , );


--B1_SCN[2] is Keyboard:inst|SCN[2]
--operation mode is normal

B1_SCN[2]_lut_out = B1_Counter[0] # !B1_Counter[1];
B1_SCN[2] = DFFEA(B1_SCN[2]_lut_out, B1_Clock_1[14], , , , , );


--B1_SCN[1] is Keyboard:inst|SCN[1]
--operation mode is normal

B1_SCN[1]_lut_out = B1_Counter[1] # !B1_Counter[0];
B1_SCN[1] = DFFEA(B1_SCN[1]_lut_out, B1_Clock_1[14], , , , , );


--B1_SCN[0] is Keyboard:inst|SCN[0]
--operation mode is normal

B1_SCN[0]_lut_out = B1_Counter[0] # B1_Counter[1];
B1_SCN[0] = DFFEA(B1_SCN[0]_lut_out, B1_Clock_1[14], , , , , );


--D1_latch_address[0] is FPGA_S51_0:inst5|latch_address[0]
--operation mode is normal

D1_latch_address[0]_lut_out = p0;
D1_latch_address[0] = DFFEA(D1_latch_address[0]_lut_out, !ALE, , , , , );


--D1_latch_address[1] is FPGA_S51_0:inst5|latch_address[1]
--operation mode is normal

D1_latch_address[1]_lut_out = p1;
D1_latch_address[1] = DFFEA(D1_latch_address[1]_lut_out, !ALE, , , , , );


--D1_latch_address[6] is FPGA_S51_0:inst5|latch_address[6]
--operation mode is normal

D1_latch_address[6]_lut_out = p6;
D1_latch_address[6] = DFFEA(D1_latch_address[6]_lut_out, !ALE, , , , , );


--D1_latch_address[5] is FPGA_S51_0:inst5|latch_address[5]
--operation mode is normal

D1_latch_address[5]_lut_out = p5;
D1_latch_address[5] = DFFEA(D1_latch_address[5]_lut_out, !ALE, , , , , );


--D1_latch_address[4] is FPGA_S51_0:inst5|latch_address[4]
--operation mode is normal

D1_latch_address[4]_lut_out = p4;
D1_latch_address[4] = DFFEA(D1_latch_address[4]_lut_out, !ALE, , , , , );


--D1_latch_address[3] is FPGA_S51_0:inst5|latch_address[3]
--operation mode is normal

D1_latch_address[3]_lut_out = p3;
D1_latch_address[3] = DFFEA(D1_latch_address[3]_lut_out, !ALE, , , , , );


--D1L05 is FPGA_S51_0:inst5|reduce_nor~45
--operation mode is normal

D1L05 = !D1_latch_address[6] & !D1_latch_address[5] & !D1_latch_address[4] & !D1_latch_address[3];


--D1_latch_address[2] is FPGA_S51_0:inst5|latch_address[2]
--operation mode is normal

D1_latch_address[2]_lut_out = p2;
D1_latch_address[2] = DFFEA(D1_latch_address[2]_lut_out, !ALE, , , , , );


--D1_latch_address[7] is FPGA_S51_0:inst5|latch_address[7]
--operation mode is normal

D1_latch_address[7]_lut_out = p7;
D1_latch_address[7] = DFFEA(D1_latch_address[7]_lut_out, !ALE, , , , , );


--D1L15 is FPGA_S51_0:inst5|reduce_nor~46
--operation mode is normal

D1L15 = D1L05 & !D1_latch_address[2] & !D1_latch_address[7];


--D1L64 is FPGA_S51_0:inst5|reduce_nor~0
--operation mode is normal

D1L64 = !D1_latch_address[0] & !D1_latch_address[1] & D1L15;


--D1L74 is FPGA_S51_0:inst5|reduce_nor~1
--operation mode is normal

D1L74 = !D1_latch_address[1] & D1_latch_address[0] & D1L15;


--D1L84 is FPGA_S51_0:inst5|reduce_nor~2
--operation mode is normal

D1L84 = !D1_latch_address[0] & D1_latch_address[1] & D1L15;


--D1L94 is FPGA_S51_0:inst5|reduce_nor~3
--operation mode is normal

D1L94 = D1_latch_address[0] & D1_latch_address[1] & D1L15;


--B1_Counter[0] is Keyboard:inst|Counter[0]
--operation mode is normal

B1_Counter[0]_lut_out = !B1_Counter[0];
B1_Counter[0] = DFFEA(B1_Counter[0]_lut_out, B1_Clock_1[14], , , , , );


--B1_Counter[1] is Keyboard:inst|Counter[1]
--operation mode is normal

B1_Counter[1]_lut_out = B1_Counter[0] $ B1_Counter[1];
B1_Counter[1] = DFFEA(B1_Counter[1]_lut_out, B1_Clock_1[14], , , , , );


--B1_Clock_1[14] is Keyboard:inst|Clock_1[14]
--operation mode is normal

B1_Clock_1[14]_lut_out = F1_unreg_res_node[14] & B1L02 # B1L12 # B1L32;
B1_Clock_1[14] = DFFEA(B1_Clock_1[14]_lut_out, clock, , , , , );


--B1_Clock_1[13] is Keyboard:inst|Clock_1[13]
--operation mode is normal

B1_Clock_1[13]_lut_out = H3_cs_buffer[13];
B1_Clock_1[13] = DFFEA(B1_Clock_1[13]_lut_out, clock, , , , , );


--B1_Clock_1[12] is Keyboard:inst|Clock_1[12]
--operation mode is normal

B1_Clock_1[12]_lut_out = H3_cs_buffer[12];
B1_Clock_1[12] = DFFEA(B1_Clock_1[12]_lut_out, clock, , , , , );


--B1_Clock_1[11] is Keyboard:inst|Clock_1[11]
--operation mode is normal

B1_Clock_1[11]_lut_out = H3_cs_buffer[11] & B1L02 # B1L12 # B1L32;
B1_Clock_1[11] = DFFEA(B1_Clock_1[11]_lut_out, clock, , , , , );


--B1L02 is Keyboard:inst|reduce_nor~127
--operation mode is normal

B1L02 = B1_Clock_1[13] # B1_Clock_1[12] # !B1_Clock_1[11] # !B1_Clock_1[14];


--B1_Clock_1[8] is Keyboard:inst|Clock_1[8]
--operation mode is normal

B1_Clock_1[8]_lut_out = H3_cs_buffer[8];
B1_Clock_1[8] = DFFEA(B1_Clock_1[8]_lut_out, clock, , , , , );


--B1_Clock_1[7] is Keyboard:inst|Clock_1[7]
--operation mode is normal

B1_Clock_1[7]_lut_out = H3_cs_buffer[7];
B1_Clock_1[7] = DFFEA(B1_Clock_1[7]_lut_out, clock, , , , , );


--B1_Clock_1[10] is Keyboard:inst|Clock_1[10]
--operation mode is normal

B1_Clock_1[10]_lut_out = H3_cs_buffer[10] & B1L02 # B1L12 # B1L32;
B1_Clock_1[10] = DFFEA(B1_Clock_1[10]_lut_out, clock, , , , , );


--B1_Clock_1[9] is Keyboard:inst|Clock_1[9]
--operation mode is normal

B1_Clock_1[9]_lut_out = H3_cs_buffer[9] & B1L02 # B1L12 # B1L32;
B1_Clock_1[9] = DFFEA(B1_Clock_1[9]_lut_out, clock, , , , , );


--B1L12 is Keyboard:inst|reduce_nor~128
--operation mode is normal

B1L12 = B1_Clock_1[8] # B1_Clock_1[7] # !B1_Clock_1[9] # !B1_Clock_1[10];


--B1_Clock_1[6] is Keyboard:inst|Clock_1[6]
--operation mode is normal

B1_Clock_1[6]_lut_out = H3_cs_buffer[6];
B1_Clock_1[6] = DFFEA(B1_Clock_1[6]_lut_out, clock, , , , , );


--B1_Clock_1[4] is Keyboard:inst|Clock_1[4]
--operation mode is normal

B1_Clock_1[4]_lut_out = H3_cs_buffer[4];
B1_Clock_1[4] = DFFEA(B1_Clock_1[4]_lut_out, clock, , , , , );


--B1_Clock_1[3] is Keyboard:inst|Clock_1[3]
--operation mode is normal

B1_Clock_1[3]_lut_out = H3_cs_buffer[3];
B1_Clock_1[3] = DFFEA(B1_Clock_1[3]_lut_out, clock, , , , , );


--B1_Clock_1[5] is Keyboard:inst|Clock_1[5]
--operation mode is normal

B1_Clock_1[5]_lut_out = H3_cs_buffer[5] & B1L02 # B1L12 # B1L32;
B1_Clock_1[5] = DFFEA(B1_Clock_1[5]_lut_out, clock, , , , , );


--B1L22 is Keyboard:inst|reduce_nor~129
--operation mode is normal

B1L22 = B1_Clock_1[6] # B1_Clock_1[4] # B1_Clock_1[3] # !B1_Clock_1[5];


--B1_Clock_1[2] is Keyboard:inst|Clock_1[2]
--operation mode is normal

B1_Clock_1[2]_lut_out = H3_cs_buffer[2];
B1_Clock_1[2] = DFFEA(B1_Clock_1[2]_lut_out, clock, , , , , );


--B1_Clock_1[1] is Keyboard:inst|Clock_1[1]
--operation mode is normal

B1_Clock_1[1]_lut_out = H3_cs_buffer[1];
B1_Clock_1[1] = DFFEA(B1_Clock_1[1]_lut_out, clock, , , , , );


--B1_Clock_1[0] is Keyboard:inst|Clock_1[0]
--operation mode is arithmetic

B1_Clock_1[0]_lut_out = !B1_Clock_1[0] & B1L42;
B1_Clock_1[0] = DFFEA(B1_Clock_1[0]_lut_out, clock, , , , , );

--H3_cout[0] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

H3_cout[0] = CARRY(B1_Clock_1[0]);


--B1L32 is Keyboard:inst|reduce_nor~130
--operation mode is normal

B1L32 = B1L22 # B1_Clock_1[2] # B1_Clock_1[1] # B1_Clock_1[0];


--H3_cs_buffer[13] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

H3_cs_buffer[13] = B1_Clock_1[13] $ (H3_cout[12]);

--H3_cout[13] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

H3_cout[13] = CARRY(B1_Clock_1[13] & H3_cout[12]);


--F1_unreg_res_node[14] is Keyboard:inst|lpm_add_sub:add_rtl_0|addcore:adder|unreg_res_node[14]
--operation mode is normal