bl.vhd

程序主要是用硬件描述语言（VHDL）实现： 4*4键盘扫描

library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY BL IS
	
	PORT
	(
		clk		: IN	STD_LOGIC;
		kin				: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		scan	: OUT	STD_LOGIC_VECTOR(3 DOWNTO 0);
		num:      OUT INTEGER RANGE 0 TO 15
	);
END BL;

ARCHITECTURE a OF BL IS
SIGNAL cnt :STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN

-----------------------------------------------------------------------------------------

READ_LIE:BLOCK

port(clk: in std_logic;
     cnt_in :  in  STD_LOGIC_VECTOR(1 DOWNTO 0);--键盘扫描行号
    lie_scan:  in  STD_LOGIC_VECTOR(3 DOWNTO 0);--列扫描信号
      led:  out integer range 0 to 15 
    );
PORT MAP(CLK=>CLK,CNT_IN=>CNT,LIE_SCAN=>KIN,LED=>NUM);
  signal cnt: std_logic_vector(1 downto 0);
BEGIN

   
  process(clk,cnt_in,lie_scan)
  begin
    cnt <= cnt_in;
  if(clk'event and clk = '1') then
      if(cnt=0) then
        if(lie_scan="1110") then
            led <= 0;
        elsif(lie_scan="1101") then
            led <= 1;
        elsif(lie_scan="1011") then
            led <= 2;
        elsif(lie_scan="0111") then
            led <= 3;
        else
            null;
        end if;
       end if;
     
    if(cnt=1) then
       if(lie_scan="1110") then
           led <= 4;
       elsif(lie_scan="1101") then
           led <= 5;
       elsif(lie_scan="1011") then
           led <= 6;
       elsif(lie_scan="0111") then
           led <= 7;
       else
           null;
       end if;
    end if;

    if(cnt=2) then
       if(lie_scan="1110") then
           led <= 8;
       elsif(lie_scan="1101") then
           led <= 9;
       elsif(lie_scan="1011") then
           led <= 10;
       elsif(lie_scan="0111") then
           led <= 11;
       else
           null;
       end if;
    end if;
    if(cnt=3) then
        if(lie_scan="1110") then
            led <= 12;
        elsif(lie_scan="1101") then
            led <= 13;
        elsif(lie_scan="1011") then
            led <= 14;
        elsif(lie_scan="0111") then
            led <= 15;
        else
            null;
        end if;
    end if;
end if;
end process;
END BLOCK READ_LIE;

----------------------------------------------------------------------------------------
OUT_HANG:BLOCK

PORT(
CLK  :  IN  STD_LOGIC;
CNT_OUT  :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
CLK_SCAN  :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0) );

PORT MAP(CLK=>CLK,CNT_OUT=>CNT,CLK_SCAN=>SCAN);

 SIGNAL  Q      :   STD_LOGIC_VECTOR(10 DOWNTO 0);
 SIGNAL  CNT,S  :   STD_LOGIC_VECTOR(1 DOWNTO 0);
 SIGNAL  SEL    :   STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN
 

 PROCESS(CLK)
 BEGIN
IF CLK'EVENT AND CLK='1' THEN
   Q<=Q+1;
END IF;
 END PROCESS;
       CNT<=Q(10 DOWNTO 9);
         
       SEL<="1110"  WHEN  S=0 ELSE
            "1101"  WHEN  S=1 ELSE
            "1011"  WHEN  S=2 ELSE
            "0111"  WHEN  S=3 ELSE
            "1111";

S<=CNT;
CNT_OUT<=CNT;
CLK_SCAN<=SEL;


END BLOCK OUT_HANG;

---------------------------------------------------------------------------------
END a;