📄 display.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+- LC97 display_data0
|
| Other LABs fed by signals
| that feed LAB 'G'
LC | | A B C D E F G H | Logic cells that feed LAB 'G':
Pin
12 -> * | - - - - - - * - | <-- data00
54 -> * | - - - - - - * - | <-- data20
29 -> * | - - - - - - * - | <-- data40
83 -> - | - - - - - - - - | <-- Display_clk
LC123-> * | - - - - - * * * | <-- display_port0
LC120-> * | - - - - - * * * | <-- display_port1
LC118-> * | - - - - - * * * | <-- display_port2
LC84 -> * | - - - - - - * - | <-- ~395~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------- LC125 display_data1
| +--------------- LC117 display_data2
| | +------------- LC115 display_data3
| | | +----------- LC123 display_port0
| | | | +--------- LC120 display_port1
| | | | | +------- LC118 display_port2
| | | | | | +----- LC116 ~323~1
| | | | | | | +--- LC114 ~347~1
| | | | | | | | +- LC113 ~371~1
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC123-> * * * * * * * * * | - - - - - * * * | <-- display_port0
LC120-> * * * - * * * * * | - - - - - * * * | <-- display_port1
LC118-> * * * - - * * * * | - - - - - * * * | <-- display_port2
LC116-> - - * - - - - - - | - - - - - - - * | <-- ~323~1
LC114-> - * - - - - - - - | - - - - - - - * | <-- ~347~1
LC113-> * - - - - - - - - | - - - - - - - * | <-- ~371~1
Pin
27 -> * - - - - - - - - | - - - - - - - * | <-- data01
41 -> - * - - - - - - - | - - - - - - - * | <-- data02
37 -> - - * - - - - - - | - - - - - - - * | <-- data03
33 -> - - - - - - - - * | - - - - - - - * | <-- data11
48 -> - - - - - - - * - | - - - - - - - * | <-- data12
52 -> - - - - - - * - - | - - - - - - - * | <-- data13
22 -> * - - - - - - - - | - - - - - - - * | <-- data21
39 -> - * - - - - - - - | - - - - - - - * | <-- data22
23 -> - - * - - - - - - | - - - - - - - * | <-- data23
25 -> - - - - - - - - * | - - - - - - - * | <-- data31
28 -> - - - - - - - * - | - - - - - - - * | <-- data32
30 -> - - - - - - * - - | - - - - - - - * | <-- data33
31 -> * - - - - - - - - | - - - - - - - * | <-- data41
11 -> - * - - - - - - - | - - - - - - - * | <-- data42
10 -> - - * - - - - - - | - - - - - - - * | <-- data43
8 -> - - - - - - - - * | - - - - - - - * | <-- data51
6 -> - - - - - - - * - | - - - - - - - * | <-- data52
5 -> - - - - - - * - - | - - - - - - - * | <-- data53
21 -> - - - - - - - - * | - - - - - - - * | <-- data61
20 -> - - - - - - - * - | - - - - - - - * | <-- data62
18 -> - - - - - - * - - | - - - - - - - * | <-- data63
16 -> - - - - - - - - * | - - - - - - - * | <-- data71
15 -> - - - - - - - * - | - - - - - - - * | <-- data72
14 -> - - - - - - * - - | - - - - - - - * | <-- data73
83 -> - - - - - - - - - | - - - - - - - - | <-- Display_clk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** EQUATIONS **
data00 : INPUT;
data01 : INPUT;
data02 : INPUT;
data03 : INPUT;
data10 : INPUT;
data11 : INPUT;
data12 : INPUT;
data13 : INPUT;
data20 : INPUT;
data21 : INPUT;
data22 : INPUT;
data23 : INPUT;
data30 : INPUT;
data31 : INPUT;
data32 : INPUT;
data33 : INPUT;
data40 : INPUT;
data41 : INPUT;
data42 : INPUT;
data43 : INPUT;
data50 : INPUT;
data51 : INPUT;
data52 : INPUT;
data53 : INPUT;
data60 : INPUT;
data61 : INPUT;
data62 : INPUT;
data63 : INPUT;
data70 : INPUT;
data71 : INPUT;
data72 : INPUT;
data73 : INPUT;
Display_clk : INPUT;
-- Node name is 'display_data0'
-- Equation name is 'display_data0', location is LC097, type is output.
display_data0 = LCELL( _EQ001 $ VCC);
_EQ001 = !_LC084 & _X001 & _X002 & _X003;
_X001 = EXP( data20 & !display_port0 & display_port1 & !display_port2);
_X002 = EXP( data40 & !display_port0 & !display_port1 & display_port2);
_X003 = EXP( data00 & !display_port0 & !display_port1 & !display_port2);
-- Node name is 'display_data1'
-- Equation name is 'display_data1', location is LC125, type is output.
display_data1 = LCELL( _EQ002 $ VCC);
_EQ002 = !_LC113 & _X004 & _X005 & _X006;
_X004 = EXP( data21 & !display_port0 & display_port1 & !display_port2);
_X005 = EXP( data41 & !display_port0 & !display_port1 & display_port2);
_X006 = EXP( data01 & !display_port0 & !display_port1 & !display_port2);
-- Node name is 'display_data2'
-- Equation name is 'display_data2', location is LC117, type is output.
display_data2 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC114 & _X007 & _X008 & _X009;
_X007 = EXP( data22 & !display_port0 & display_port1 & !display_port2);
_X008 = EXP( data42 & !display_port0 & !display_port1 & display_port2);
_X009 = EXP( data02 & !display_port0 & !display_port1 & !display_port2);
-- Node name is 'display_data3'
-- Equation name is 'display_data3', location is LC115, type is output.
display_data3 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC116 & _X010 & _X011 & _X012;
_X010 = EXP( data23 & !display_port0 & display_port1 & !display_port2);
_X011 = EXP( data43 & !display_port0 & !display_port1 & display_port2);
_X012 = EXP( data03 & !display_port0 & !display_port1 & !display_port2);
-- Node name is 'display_port0' = 'dport_num0'
-- Equation name is 'display_port0', location is LC123, type is output.
display_port0 = TFFE( VCC, GLOBAL( Display_clk), VCC, VCC, VCC);
-- Node name is 'display_port1' = 'dport_num1'
-- Equation name is 'display_port1', location is LC120, type is output.
display_port1 = TFFE( display_port0, GLOBAL( Display_clk), VCC, VCC, VCC);
-- Node name is 'display_port2' = 'dport_num2'
-- Equation name is 'display_port2', location is LC118, type is output.
display_port2 = TFFE( _EQ005, GLOBAL( Display_clk), VCC, VCC, VCC);
_EQ005 = display_port0 & display_port1;
-- Node name is '~323~1'
-- Equation name is '~323~1', location is LC116, type is buried.
-- synthesized logic cell
_LC116 = LCELL( _EQ006 $ GND);
_EQ006 = data73 & display_port0 & display_port1 & display_port2
# data33 & display_port0 & display_port1 & !display_port2
# data53 & display_port0 & !display_port1 & display_port2
# data63 & !display_port0 & display_port1 & display_port2
# data13 & display_port0 & !display_port1 & !display_port2;
-- Node name is '~347~1'
-- Equation name is '~347~1', location is LC114, type is buried.
-- synthesized logic cell
_LC114 = LCELL( _EQ007 $ GND);
_EQ007 = data72 & display_port0 & display_port1 & display_port2
# data32 & display_port0 & display_port1 & !display_port2
# data52 & display_port0 & !display_port1 & display_port2
# data62 & !display_port0 & display_port1 & display_port2
# data12 & display_port0 & !display_port1 & !display_port2;
-- Node name is '~371~1'
-- Equation name is '~371~1', location is LC113, type is buried.
-- synthesized logic cell
_LC113 = LCELL( _EQ008 $ GND);
_EQ008 = data71 & display_port0 & display_port1 & display_port2
# data31 & display_port0 & display_port1 & !display_port2
# data51 & display_port0 & !display_port1 & display_port2
# data61 & !display_port0 & display_port1 & display_port2
# data11 & display_port0 & !display_port1 & !display_port2;
-- Node name is '~395~1'
-- Equation name is '~395~1', location is LC084, type is buried.
-- synthesized logic cell
_LC084 = LCELL( _EQ009 $ GND);
_EQ009 = data70 & display_port0 & display_port1 & display_port2
# data30 & display_port0 & display_port1 & !display_port2
# data50 & display_port0 & !display_port1 & display_port2
# data60 & !display_port0 & display_port1 & display_port2
# data10 & display_port0 & !display_port1 & !display_port2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\exp-sample\module\display.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000E' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 20,200K
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