📄 display.rpt
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Project Information e:\exp-sample\module\display.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 12/07/2004 23:40:25
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
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their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DISPLAY
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
display EPM7128ELC84-7 33 7 0 11 12 8 %
User Pins: 33 7 0
Project Information e:\exp-sample\module\display.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'Display_clk' chosen for auto global Clock
Project Information e:\exp-sample\module\display.rpt
** FILE HIERARCHY **
|lpm_add_sub:53|
|lpm_add_sub:53|addcore:adder|
|lpm_add_sub:53|addcore:adder|addcore:adder0|
|lpm_add_sub:53|altshift:result_ext_latency_ffs|
|lpm_add_sub:53|altshift:carry_ext_latency_ffs|
|lpm_add_sub:53|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\exp-sample\module\display.rpt
display
***** Logic for device 'display' compiled without errors.
Device: EPM7128ELC84-7
Device Options:
Turbo Bit = ON
Security Bit = OFF
MultiVolt I/O = OFF
d d d d
i i i i
D s s s s
i p p p p
s l l l l
p R R a a a a
l E E y y y y
d d d d d d d V a S S _ _ _ _
a a a a a a a C y E E d V p p p
t t t t t t t C _ R R a C o o o
a a a a G a a a I G G G c G V V t C r r r
4 4 5 5 N 5 5 6 N N N N l N E E a I t t t
2 3 0 1 D 2 3 0 T D D D k D D D 1 O 0 1 2
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
data00 | 12 74 | display_data2
VCCIO | 13 73 | display_data3
data73 | 14 72 | GND
data72 | 15 71 | RESERVED
data71 | 16 70 | RESERVED
data70 | 17 69 | RESERVED
data63 | 18 68 | RESERVED
GND | 19 67 | RESERVED
data62 | 20 66 | VCCIO
data61 | 21 65 | RESERVED
data21 | 22 EPM7128ELC84-7 64 | RESERVED
data23 | 23 63 | display_data0
data30 | 24 62 | RESERVED
data31 | 25 61 | RESERVED
VCCIO | 26 60 | RESERVED
data01 | 27 59 | GND
data32 | 28 58 | RESERVED
data40 | 29 57 | RESERVED
data33 | 30 56 | RESERVED
data41 | 31 55 | RESERVED
GND | 32 54 | data20
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
d d R R d V d R d G V R R R G d R R R d V
a a E E a C a E a N C E E E N a E E E a C
t t S S t C t S t D C S S S D t S S S t C
a a E E a I a E a I E E E a E E E a I
1 1 R R 0 O 2 R 0 N R R R 1 R R R 1 O
1 0 V V 3 2 V 2 T V V V 2 V V V 3
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
C: LC33 - LC48 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%)
D: LC49 - LC64 0/16( 0%) 5/ 8( 62%) 0/16( 0%) 0/36( 0%)
E: LC65 - LC80 0/16( 0%) 2/ 8( 25%) 0/16( 0%) 0/36( 0%)
F: LC81 - LC96 1/16( 6%) 1/ 8( 12%) 1/16( 6%) 8/36( 22%)
G: LC97 - LC112 1/16( 6%) 1/ 8( 12%) 3/16( 18%) 7/36( 19%)
H: LC113 - LC128 9/16( 56%) 6/ 8( 75%) 12/16( 75%) 30/36( 83%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 39/64 ( 60%)
Total logic cells used: 11/128 ( 8%)
Total shareable expanders used: 12/128 ( 9%)
Total Turbo logic cells used: 11/128 ( 8%)
Total shareable expanders not available (n/a): 4/128 ( 3%)
Average fan-in: 6.27
Total fan-in: 69
Total input pins required: 33
Total fast input logic cells required: 0
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 11
Total flipflops required: 3
Total product terms required: 39
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 12
Synthesized logic cells: 4/ 128 ( 3%)
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
12 (3) (A) INPUT 0 0 0 0 0 1 0 data00
27 (43) (C) INPUT 0 0 0 0 0 1 0 data01
41 (49) (D) INPUT 0 0 0 0 0 1 0 data02
37 (56) (D) INPUT 0 0 0 0 0 1 0 data03
34 (61) (D) INPUT 0 0 0 0 0 0 1 data10
33 (64) (D) INPUT 0 0 0 0 0 0 1 data11
48 (72) (E) INPUT 0 0 0 0 0 0 1 data12
52 (80) (E) INPUT 0 0 0 0 0 0 1 data13
54 (83) (F) INPUT 0 0 0 0 0 1 0 data20
22 (17) (B) INPUT 0 0 0 0 0 1 0 data21
39 (53) (D) INPUT 0 0 0 0 0 1 0 data22
23 (48) (C) INPUT 0 0 0 0 0 1 0 data23
24 (46) (C) INPUT 0 0 0 0 0 0 1 data30
25 (45) (C) INPUT 0 0 0 0 0 0 1 data31
28 (40) (C) INPUT 0 0 0 0 0 0 1 data32
30 (37) (C) INPUT 0 0 0 0 0 0 1 data33
29 (38) (C) INPUT 0 0 0 0 0 1 0 data40
31 (35) (C) INPUT 0 0 0 0 0 1 0 data41
11 (5) (A) INPUT 0 0 0 0 0 1 0 data42
10 (6) (A) INPUT 0 0 0 0 0 1 0 data43
9 (8) (A) INPUT 0 0 0 0 0 0 1 data50
8 (11) (A) INPUT 0 0 0 0 0 0 1 data51
6 (13) (A) INPUT 0 0 0 0 0 0 1 data52
5 (14) (A) INPUT 0 0 0 0 0 0 1 data53
4 (16) (A) INPUT 0 0 0 0 0 0 1 data60
21 (19) (B) INPUT 0 0 0 0 0 0 1 data61
20 (21) (B) INPUT 0 0 0 0 0 0 1 data62
18 (24) (B) INPUT 0 0 0 0 0 0 1 data63
17 (25) (B) INPUT 0 0 0 0 0 0 1 data70
16 (27) (B) INPUT 0 0 0 0 0 0 1 data71
15 (29) (B) INPUT 0 0 0 0 0 0 1 data72
14 (32) (B) INPUT 0 0 0 0 0 0 1 data73
83 - - INPUT G 0 0 0 0 0 0 0 Display_clk
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
63 97 G OUTPUT t 3 0 0 3 4 0 0 display_data0
79 125 H OUTPUT t 3 0 0 3 4 0 0 display_data1
74 117 H OUTPUT t 3 0 0 3 4 0 0 display_data2
73 115 H OUTPUT t 3 0 0 3 4 0 0 display_data3
77 123 H FF + t 0 0 0 0 0 6 4 display_port0 (:43)
76 120 H FF + t 0 0 0 0 1 5 4 display_port1 (:42)
75 118 H FF + t 0 0 0 0 2 4 4 display_port2 (:41)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 116 H SOFT s t 1 0 1 5 3 1 0 ~323~1
- 114 H SOFT s t 1 0 1 5 3 1 0 ~347~1
- 113 H SOFT s t 1 0 1 5 3 1 0 ~371~1
- 84 F SOFT s t 1 0 1 5 3 1 0 ~395~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\exp-sample\module\display.rpt
display
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+- LC84 ~395~1
|
| Other LABs fed by signals
| that feed LAB 'F'
LC | | A B C D E F G H | Logic cells that feed LAB 'F':
Pin
34 -> * | - - - - - * - - | <-- data10
24 -> * | - - - - - * - - | <-- data30
9 -> * | - - - - - * - - | <-- data50
4 -> * | - - - - - * - - | <-- data60
17 -> * | - - - - - * - - | <-- data70
83 -> - | - - - - - - - - | <-- Display_clk
LC123-> * | - - - - - * * * | <-- display_port0
LC120-> * | - - - - - * * * | <-- display_port1
LC118-> * | - - - - - * * * | <-- display_port2
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