display.vhd

数码扫描显示转换模块

------------------------------------------------------------------------
--			译码显示电路
--		输入	Display_clk为扫描时钟，频率应大于10K
--				data0～data7	分别为数码管0到7的以BCD码表示的显示值
--		输出	display_data	数码管上以BCD码表示的显示值
--				display_port	以BCD码表示的数码管位置共有八个为0～7
--
--         Author:                 Senor-Xu
--
--         Filename:               Display.vhd
--
--         Date of Creation:       2003-10-08
--
--         Version:                1.0
--
--         Date of Latest Version: 2004-12-06
-------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity display is port
	(
		Display_clk							:in		std_logic;
		data0,data1,data2,data3,data4,data5,data6,data7		:in		std_logic_vector(3 downto 0);
		display_data		:out	std_logic_vector(3 downto 0);
		display_port		:out	std_logic_vector(2 downto 0)
	);
end display;

architecture rtl_display of display is
signal dport_num	:	std_logic_vector(2 downto 0);
begin
	process(display_clk)
	begin
		if rising_edge(display_clk) then
			dport_num<=dport_num+1;
		end if;
	end process;
	process(dport_num)
	begin
		case dport_num is
			when "000" =>display_data<=data0; 
			when "001" =>display_data<=data1; 
			when "010" =>display_data<=data2; 
			when "011" =>display_data<=data3; 
			when "100" =>display_data<=data4; 
			when "101" =>display_data<=data5; 
			when "110" =>display_data<=data6; 
			when "111" =>display_data<=data7; 
			when others =>display_data<="0000"; 
		end case;
	end process;
	display_port<=dport_num;
end;