key.tan.qmsg

用VHDL实现的键盘扫描程序 可以稍微修改就可使用

{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in clk_out clk_out~reg0 9.700 ns register " "Info: tco from clock \"clk_in\" to destination pin \"clk_out\" through register \"clk_out~reg0\" is 9.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk_in 1 CLK PIN_79 40 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_79; Fanout = 40; CLK Node = 'clk_in'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_in } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns clk_out~reg0 2 REG LC8_C19 2 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_C19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.000 ns" { clk_in clk_out~reg0 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in clk_out~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns + Longest register pin " "Info: + Longest register to pin delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk_out~reg0 1 REG LC8_C19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_C19; Fanout = 2; REG Node = 'clk_out~reg0'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_out~reg0 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.900 ns) 4.900 ns clk_out 2 PIN PIN_198 0 " "Info: 2: + IC(1.000 ns) + CELL(3.900 ns) = 4.900 ns; Loc. = PIN_198; Fanout = 0; PIN Node = 'clk_out'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.900 ns" { clk_out~reg0 clk_out } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 79.59 % " "Info: Total cell delay = 3.900 ns ( 79.59 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 20.41 % " "Info: Total interconnect delay = 1.000 ns ( 20.41 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.900 ns" { clk_out~reg0 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.900 ns" { clk_out~reg0 clk_out } { 0.000ns 1.000ns } { 0.000ns 3.900ns } } }  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in clk_out~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out clk_out~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.900 ns" { clk_out~reg0 clk_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.900 ns" { clk_out~reg0 clk_out } { 0.000ns 1.000ns } { 0.000ns 3.900ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "temp_data_in_h\[1\] data_in_h\[1\] clk_in 0.900 ns register " "Info: th for register \"temp_data_in_h\[1\]\" (data pin = \"data_in_h\[1\]\", clock pin = \"clk_in\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk_in 1 CLK PIN_79 40 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_79; Fanout = 40; CLK Node = 'clk_in'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_in } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns temp_data_in_h\[1\] 2 REG LC6_C16 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC6_C16; Fanout = 1; REG Node = 'temp_data_in_h\[1\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.000 ns" { clk_in temp_data_in_h[1] } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in temp_data_in_h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out temp_data_in_h[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns data_in_h\[1\] 1 PIN PIN_80 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_80; Fanout = 1; PIN Node = 'data_in_h\[1\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { data_in_h[1] } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.900 ns) 4.400 ns temp_data_in_h\[1\] 2 REG LC6_C16 1 " "Info: 2: + IC(1.600 ns) + CELL(0.900 ns) = 4.400 ns; Loc. = LC6_C16; Fanout = 1; REG Node = 'temp_data_in_h\[1\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.500 ns" { data_in_h[1] temp_data_in_h[1] } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 63.64 % " "Info: Total cell delay = 2.800 ns ( 63.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 36.36 % " "Info: Total interconnect delay = 1.600 ns ( 36.36 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.400 ns" { data_in_h[1] temp_data_in_h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.400 ns" { data_in_h[1] data_in_h[1]~out temp_data_in_h[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in temp_data_in_h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out temp_data_in_h[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.400 ns" { data_in_h[1] temp_data_in_h[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.400 ns" { data_in_h[1] data_in_h[1]~out temp_data_in_h[1] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 11 09:16:20 2005 " "Info: Processing ended: Thu Aug 11 09:16:20 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}