key.tan.qmsg

用VHDL实现的键盘扫描程序 可以稍微修改就可使用

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_in " "Info: Assuming node \"clk_in\" is an undefined clock" {  } { { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_in" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] register lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] 57.47 MHz 17.4 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 57.47 MHz between source register \"lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]\" and destination register \"lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]\" (period= 17.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.200 ns + Longest register register " "Info: + Longest register to register delay is 15.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC3_C15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_C15; Fanout = 3; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 3.200 ns reduce_or~117 2 COMB LC3_C16 1 " "Info: 2: + IC(1.800 ns) + CELL(1.400 ns) = 3.200 ns; Loc. = LC3_C16; Fanout = 1; COMB Node = 'reduce_or~117'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.200 ns" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] reduce_or~117 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 4.500 ns reduce_or~107 3 COMB LC4_C16 1 " "Info: 3: + IC(0.000 ns) + CELL(1.300 ns) = 4.500 ns; Loc. = LC4_C16; Fanout = 1; COMB Node = 'reduce_or~107'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "1.300 ns" { reduce_or~117 reduce_or~107 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 8.200 ns temp_couter~258 4 COMB LC1_C14 4 " "Info: 4: + IC(1.800 ns) + CELL(1.900 ns) = 8.200 ns; Loc. = LC1_C14; Fanout = 4; COMB Node = 'temp_couter~258'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.700 ns" { reduce_or~107 temp_couter~258 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.900 ns) 12.000 ns temp_couter~261 5 COMB LC4_C13 11 " "Info: 5: + IC(1.900 ns) + CELL(1.900 ns) = 12.000 ns; Loc. = LC4_C13; Fanout = 11; COMB Node = 'temp_couter~261'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.800 ns" { temp_couter~258 temp_couter~261 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 15.200 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] 6 REG LC7_C15 4 " "Info: 6: + IC(1.800 ns) + CELL(1.400 ns) = 15.200 ns; Loc. = LC7_C15; Fanout = 4; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.200 ns" { temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.900 ns 51.97 % " "Info: Total cell delay = 7.900 ns ( 51.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.300 ns 48.03 % " "Info: Total interconnect delay = 7.300 ns ( 48.03 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "15.200 ns" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] reduce_or~117 reduce_or~107 temp_couter~258 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.200 ns" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] reduce_or~117 reduce_or~107 temp_couter~258 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 1.800ns 0.000ns 1.800ns 1.900ns 1.800ns } { 0.000ns 1.400ns 1.300ns 1.900ns 1.900ns 1.400ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk_in 1 CLK PIN_79 40 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_79; Fanout = 40; CLK Node = 'clk_in'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_in } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\] 2 REG LC7_C15 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_C15; Fanout = 4; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[6\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.000 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk_in 1 CLK PIN_79 40 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_79; Fanout = 40; CLK Node = 'clk_in'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_in } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC3_C15 3 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC3_C15; Fanout = 3; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[2\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.000 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "15.200 ns" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] reduce_or~117 reduce_or~107 temp_couter~258 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "15.200 ns" { lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] reduce_or~117 reduce_or~107 temp_couter~258 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 1.800ns 0.000ns 1.800ns 1.900ns 1.800ns } { 0.000ns 1.400ns 1.300ns 1.900ns 1.900ns 1.400ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[6] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] stop clk_in 10.800 ns register " "Info: tsu for register \"lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]\" (data pin = \"stop\", clock pin = \"clk_in\") is 10.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.400 ns + Longest pin register " "Info: + Longest pin to register delay is 13.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns stop 1 PIN PIN_182 3 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_182; Fanout = 3; PIN Node = 'stop'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { stop } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(1.900 ns) 5.500 ns temp_data_in_l\[0\]~7 2 COMB LC1_C19 18 " "Info: 2: + IC(1.700 ns) + CELL(1.900 ns) = 5.500 ns; Loc. = LC1_C19; Fanout = 18; COMB Node = 'temp_data_in_l\[0\]~7'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.600 ns" { stop temp_data_in_l[0]~7 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.900 ns) 10.200 ns temp_couter~261 3 COMB LC4_C13 11 " "Info: 3: + IC(2.800 ns) + CELL(1.900 ns) = 10.200 ns; Loc. = LC4_C13; Fanout = 11; COMB Node = 'temp_couter~261'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "4.700 ns" { temp_data_in_l[0]~7 temp_couter~261 } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 13.400 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 4 REG LC2_C15 4 " "Info: 4: + IC(1.800 ns) + CELL(1.400 ns) = 13.400 ns; Loc. = LC2_C15; Fanout = 4; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.200 ns" { temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.100 ns 52.99 % " "Info: Total cell delay = 7.100 ns ( 52.99 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.300 ns 47.01 % " "Info: Total interconnect delay = 6.300 ns ( 47.01 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "13.400 ns" { stop temp_data_in_l[0]~7 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.400 ns" { stop stop~out temp_data_in_l[0]~7 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.700ns 2.800ns 1.800ns } { 0.000ns 1.900ns 1.900ns 1.900ns 1.400ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk_in 1 CLK PIN_79 40 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_79; Fanout = 40; CLK Node = 'clk_in'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "" { clk_in } "NODE_NAME" } "" } } { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\] 2 REG LC2_C15 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC2_C15; Fanout = 4; REG Node = 'lpm_counter:temp_couter_rtl_1\|alt_counter_f10ke:wysi_counter\|q\[1\]'" {  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "2.000 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}  } { { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "13.400 ns" { stop temp_data_in_l[0]~7 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.400 ns" { stop stop~out temp_data_in_l[0]~7 temp_couter~261 lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 1.700ns 2.800ns 1.800ns } { 0.000ns 1.900ns 1.900ns 1.900ns 1.400ns } } } { "E:/test_fpga/5/db/key_cmp.qrpt" "" { Report "E:/test_fpga/5/db/key_cmp.qrpt" Compiler "key" "UNKNOWN" "V1" "E:/test_fpga/5/db/key.quartus_db" { Floorplan "E:/test_fpga/5/" "" "3.900 ns" { clk_in lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.900 ns" { clk_in clk_in~out lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter|q[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0}