key.map.qmsg

用VHDL实现的键盘扫描程序 可以稍微修改就可使用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Aug 11 09:16:00 2005 " "Info: Processing started: Thu Aug 11 09:16:00 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off key -c key " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key -c key" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fren_cout.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fren_cout.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fren_cout-a " "Info: Found design unit 1: fren_cout-a" {  } { { "fren_cout.vhd" "" { Text "E:/test_fpga/5/fren_cout.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fren_cout " "Info: Found entity 1: fren_cout" {  } { { "fren_cout.vhd" "" { Text "E:/test_fpga/5/fren_cout.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "divd_fren.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file divd_fren.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 divd_fren-a " "Info: Found design unit 1: divd_fren-a" {  } { { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 19 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 divd_fren " "Info: Found entity 1: divd_fren" {  } { { "divd_fren.vhd" "" { Text "E:/test_fpga/5/divd_fren.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "divd_fren " "Info: Elaborating entity \"divd_fren\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "temp_couter1\[0\]~120 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"temp_couter1\[0\]~120\"" {  } { { "divd_fren.vhd" "temp_couter1\[0\]~120" { Text "E:/test_fpga/5/divd_fren.vhd" 24 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "temp_couter\[0\]~120 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: \"temp_couter\[0\]~120\"" {  } { { "divd_fren.vhd" "temp_couter\[0\]~120" { Text "E:/test_fpga/5/divd_fren.vhd" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 250 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "20 " "Info: Implemented 20 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "52 " "Info: Implemented 52 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 11 09:16:03 2005 " "Info: Processing ended: Thu Aug 11 09:16:03 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}