key.map.rpt

来自「用VHDL实现的键盘扫描程序 可以稍微修改就可使用」· RPT 代码 · 共 268 行 · 第 1/2 页

;     -- Total 3-input functions    ; 2       ;
;     -- Total 2-input functions    ; 20      ;
;     -- Total 1-input functions    ; 0       ;
;     -- Total 0-input functions    ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 34      ;
; Total logic cells in carry chains ; 16      ;
; I/O pins                          ; 21      ;
; Maximum fan-out node              ; clk_in  ;
; Maximum fan-out                   ; 34      ;
; Total fan-out                     ; 185     ;
; Average fan-out                   ; 2.53    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                      ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------+
; |divd_fren                             ; 52 (36)     ; 34           ; 0           ; 21   ; 18 (18)      ; 16 (16)           ; 18 (2)           ; 16 (0)          ; |divd_fren                                                               ;
;    |lpm_counter:temp_couter1_rtl_0|    ; 8 (0)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |divd_fren|lpm_counter:temp_couter1_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 8 (8)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |divd_fren|lpm_counter:temp_couter1_rtl_0|alt_counter_f10ke:wysi_counter ;
;    |lpm_counter:temp_couter_rtl_1|     ; 8 (0)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (0)            ; 8 (0)           ; |divd_fren|lpm_counter:temp_couter_rtl_1                                 ;
;       |alt_counter_f10ke:wysi_counter| ; 8 (8)       ; 8            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |divd_fren|lpm_counter:temp_couter_rtl_1|alt_counter_f10ke:wysi_counter  ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 34    ;
; Number of registers using Synchronous Clear  ; 16    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 17    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:temp_couter1_rtl_0 ;
+------------------------+---------+----------------------------------------------+
; Parameter Name         ; Value   ; Type                                         ;
+------------------------+---------+----------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                               ;
; LPM_WIDTH              ; 8       ; Untyped                                      ;
; LPM_DIRECTION          ; UP      ; Untyped                                      ;
; LPM_MODULUS            ; 0       ; Untyped                                      ;
; LPM_AVALUE             ; UNUSED  ; Untyped                                      ;
; LPM_SVALUE             ; UNUSED  ; Untyped                                      ;
; DEVICE_FAMILY          ; FLEX10K ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                      ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                           ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                           ;
; CARRY_CNT_EN           ; SMART   ; Untyped                                      ;
; LABWIDE_SCLR           ; ON      ; Untyped                                      ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                                      ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                                      ;
+------------------------+---------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:temp_couter_rtl_1 ;
+------------------------+---------+---------------------------------------------+
; Parameter Name         ; Value   ; Type                                        ;
+------------------------+---------+---------------------------------------------+
; AUTO_CARRY_CHAINS      ; ON      ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS   ; OFF     ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON      ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF     ; IGNORE_CASCADE                              ;
; LPM_WIDTH              ; 8       ; Untyped                                     ;
; LPM_DIRECTION          ; UP      ; Untyped                                     ;
; LPM_MODULUS            ; 0       ; Untyped                                     ;
; LPM_AVALUE             ; UNUSED  ; Untyped                                     ;
; LPM_SVALUE             ; UNUSED  ; Untyped                                     ;
; DEVICE_FAMILY          ; FLEX10K ; Untyped                                     ;
; CARRY_CHAIN            ; MANUAL  ; Untyped                                     ;
; CARRY_CHAIN_LENGTH     ; 48      ; CARRY_CHAIN_LENGTH                          ;
; NOT_GATE_PUSH_BACK     ; ON      ; NOT_GATE_PUSH_BACK                          ;
; CARRY_CNT_EN           ; SMART   ; Untyped                                     ;
; LABWIDE_SCLR           ; ON      ; Untyped                                     ;
; USE_NEW_VERSION        ; TRUE    ; Untyped                                     ;
; CBXI_PARAMETER         ; NOTHING ; Untyped                                     ;
+------------------------+---------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/test_fpga/5/key.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Aug 11 09:16:00 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off key -c key
Info: Found 2 design units, including 1 entities, in source file fren_cout.vhd
    Info: Found design unit 1: fren_cout-a
    Info: Found entity 1: fren_cout
Info: Found 2 design units, including 1 entities, in source file divd_fren.vhd
    Info: Found design unit 1: divd_fren-a
    Info: Found entity 1: divd_fren
Info: Elaborating entity "divd_fren" for the top level hierarchy
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "temp_couter1[0]~120"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: "temp_couter[0]~120"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 20 input pins
    Info: Implemented 1 output pins
    Info: Implemented 52 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Aug 11 09:16:03 2005
    Info: Elapsed time: 00:00:04