trans4_16.vho

看了好多网了

SIGNAL Mux_a370_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a370_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a373_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a376_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a379_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a382_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a385_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL in4_a0_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL in4_a3_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL in4_a2_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL in4_a1_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL Mux_a340_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a343_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a346_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a349_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a352_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a355_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a358_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a361_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a364_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a367_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a370_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a373_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a376_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a379_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a382_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL Mux_a385_I_modesel : std_logic_vector(12 DOWNTO 0);
SIGNAL out16_a0_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a1_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a2_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a3_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a4_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a5_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a6_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a7_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a8_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a9_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a10_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a11_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a12_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a13_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a14_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL out16_a15_a_aI_modesel : std_logic_vector(8 DOWNTO 0);
SIGNAL in4_a0_a_adataout : std_logic;
SIGNAL in4_a3_a_adataout : std_logic;
SIGNAL in4_a2_a_adataout : std_logic;
SIGNAL in4_a1_a_adataout : std_logic;
SIGNAL Mux_a340 : std_logic;
SIGNAL Mux_a343 : std_logic;
SIGNAL Mux_a346 : std_logic;
SIGNAL Mux_a349 : std_logic;
SIGNAL Mux_a352 : std_logic;
SIGNAL Mux_a355 : std_logic;
SIGNAL Mux_a358 : std_logic;
SIGNAL Mux_a361 : std_logic;
SIGNAL Mux_a364 : std_logic;
SIGNAL Mux_a367 : std_logic;
SIGNAL Mux_a370 : std_logic;
SIGNAL Mux_a373 : std_logic;
SIGNAL Mux_a376 : std_logic;
SIGNAL Mux_a379 : std_logic;
SIGNAL Mux_a382 : std_logic;
SIGNAL Mux_a385 : std_logic;
SIGNAL ALT_INV_in4_a1_a_adataout : std_logic;
SIGNAL ALT_INV_in4_a0_a_adataout : std_logic;
SIGNAL ALT_INV_in4_a2_a_adataout : std_logic;
SIGNAL ALT_INV_in4_a3_a_adataout : std_logic;
COMPONENT max_mcell
PORT (
	clk : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	pexpin : IN STD_LOGIC;
	fpin : IN STD_LOGIC;
	pterm0 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pterm1 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pterm2 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pterm3 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pterm4 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pterm5 : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pxor : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pclk : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	pena : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	paclr : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	papre : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
	dataout : OUT STD_LOGIC;
	pexpout : OUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(12 DOWNTO 0));
END COMPONENT;

COMPONENT max_io
PORT (
	datain : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	dataout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	MODESEL : IN STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT;