trans4_16.vho

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version"

-- DATE "08/13/2005 18:52:47"

-- 
-- Device: Altera EPM7128SLC84-15 Package PLCC84
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	trans4_16 IS
    PORT (
	in4 : IN std_logic_vector(3 DOWNTO 0);
	out16 : OUT std_logic_vector(15 DOWNTO 0)
	);
END trans4_16;

ARCHITECTURE structure OF trans4_16 IS
SIGNAL GNDs : std_logic_vector(255 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(255 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_in4 : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_out16 : std_logic_vector(15 DOWNTO 0);
SIGNAL Mux_a340_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a340_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a343_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a346_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a349_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a352_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a355_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a358_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a361_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a364_I_papre_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm0_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm1_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm2_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm3_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm4_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pterm5_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pxor_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pclk_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_pena_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_paclr_bus : std_logic_vector(51 DOWNTO 0);
SIGNAL Mux_a367_I_papre_bus : std_logic_vector(51 DOWNTO 0);