trans4_16_pt_vhd.tcl

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## Copyright (C) 1991-2005 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions 
## and other software and tools, and its AMPP partner logic       
## functions, and any output files any of the foregoing           
## (including device programming or simulation files), and any    
## associated documentation or information are expressly subject  
## to the terms and conditions of the Altera Program License      
## Subscription Agreement, Altera MegaCore Function License       
## Agreement, or other applicable license agreement, including,   
## without limitation, that your use is for the sole purpose of   
## programming logic devices manufactured by Altera and sold by   
## Altera or its authorized distributors.  Please refer to the    
## applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version"

## DATE "08/13/2005 18:52:47"

## 
## Device: Altera EPM7128SLC84-15 Package PLCC84
## 

## 
## This Tcl script should be used for PrimeTime (VHDL) only
## 

## This file can be sourced in primetime

set report_default_significant_digits 3
set hierarchy_separator .

set quartus_root "d:/altera/quartus50/"
set search_path [list . [format "%s%s" $quartus_root "eda/synopsys/primetime/lib"]  ]

set link_path [list *  max_asynch_io_lib.db max_mcell_register_lib.db  max_asynch_mcell_lib.db max_asynch_sexp_lib.db  alt_vtl.db]

read_vhdl  -vhdl_compiler  max_all_pt.vhd 

##########################
## DESIGN ENTRY SECTION ##
##########################

read_vhdl  -vhdl_compiler trans4_16.vho
current_design trans4_16
link
## Set variable timing_propagate_single_condition_min_slew to false only for versions 2004.06 and earlier
regexp {([1-9][0-9][0-9][0-9]\.[0-9][0-9])} $sh_product_version dummy version
if { [string compare "2004.06" $version ] != -1 } {
   set timing_propagate_single_condition_min_slew false
}
set_operating_conditions -analysis_type single
read_sdf trans4_16_vhd.sdo

################################
## TIMING CONSTRAINTS SECTION ##
################################


## Start clock definition ##
## End clock definition ##

## Start create collections ##
## End create collections ##

## Start global settings ##
## End global settings ##

## Start collection commands definition ##

## End collection commands definition ##

## Start individual pin commands definition ##
## End individual pin commands definition ##

## Start Output pin capacitance definition ##
# Warning: using default load capacitance for TTL output port
set_load 30 [get_ports { out16[0] out16[1] out16[2] out16[3] out16[4] out16[5] out16[6] out16[7] out16[8] out16[9] out16[10] out16[11] out16[12] out16[13] out16[14] out16[15] } ]
## End Output pin capacitance definition ##

## Start clock uncertainty definition ##
## End clock uncertainty definition ##

## Start Multicycle and Cut Path definition ##
## End Multicycle and Cut Path definition ##

## Destroy Collections ##

update_timing